soc/amd/picasso: Drop mainboard_romstage_entry_s3
[coreboot.git] / src / soc / amd / picasso / romstage.c
blob0a337e7720343634b4ed2cccfe3d60ad0aa4bf4f
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <arch/cpu.h>
4 #include <acpi/acpi.h>
5 #include <cpu/x86/cache.h>
6 #include <cpu/amd/mtrr.h>
7 #include <console/uart.h>
8 #include <cbmem.h>
9 #include <commonlib/helpers.h>
10 #include <console/console.h>
11 #include <program_loading.h>
12 #include <elog.h>
13 #include <soc/memmap.h>
14 #include <soc/mrc_cache.h>
15 #include <types.h>
16 #include "chip.h"
17 #include <fsp/api.h>
19 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
21 FSP_M_CONFIG *mcfg = &mupd->FspmConfig;
22 const config_t *config = config_of_soc();
24 mupd->FspmArchUpd.NvsBufferPtr = soc_fill_mrc_cache();
26 mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS;
27 mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE;
28 mcfg->bert_size = CONFIG_ACPI_BERT_SIZE;
29 mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
30 mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM);
31 mcfg->serial_port_stride = CONFIG(DRIVERS_UART_8250MEM_32) ? 4 : 1;
32 mcfg->serial_port_baudrate = get_uart_baudrate();
33 mcfg->serial_port_refclk = uart_platform_refclk();
35 mcfg->system_config = config->system_config;
37 if ((config->slow_ppt_limit) &&
38 (config->fast_ppt_limit) &&
39 (config->slow_ppt_time_constant) &&
40 (config->stapm_time_constant)) {
41 mcfg->slow_ppt_limit = config->slow_ppt_limit;
42 mcfg->fast_ppt_limit = config->fast_ppt_limit;
43 mcfg->slow_ppt_time_constant = config->slow_ppt_time_constant;
44 mcfg->stapm_time_constant = config->stapm_time_constant;
47 mcfg->sustained_power_limit = config->sustained_power_limit;
48 mcfg->prochot_l_deassertion_ramp_time = config->prochot_l_deassertion_ramp_time;
49 mcfg->thermctl_limit = config->thermctl_limit;
50 mcfg->psi0_current_limit = config->psi0_current_limit;
51 mcfg->psi0_soc_current_limit = config->psi0_soc_current_limit;
52 mcfg->vddcr_soc_voltage_margin = config->vddcr_soc_voltage_margin;
53 mcfg->vddcr_vdd_voltage_margin = config->vddcr_vdd_voltage_margin;
54 mcfg->vrm_maximum_current_limit = config->vrm_maximum_current_limit;
55 mcfg->vrm_soc_maximum_current_limit = config->vrm_soc_maximum_current_limit;
56 mcfg->vrm_current_limit = config->vrm_current_limit;
57 mcfg->vrm_soc_current_limit = config->vrm_soc_current_limit;
58 mcfg->sb_tsi_alert_comparator_mode_en = config->sb_tsi_alert_comparator_mode_en;
59 mcfg->core_dldo_bypass = config->core_dldo_bypass;
60 mcfg->min_soc_vid_offset = config->min_soc_vid_offset;
61 mcfg->aclk_dpm0_freq_400MHz = config->aclk_dpm0_freq_400MHz;
62 mcfg->telemetry_vddcr_vdd_slope = config->telemetry_vddcr_vdd_slope;
63 mcfg->telemetry_vddcr_vdd_offset = config->telemetry_vddcr_vdd_offset;
64 mcfg->telemetry_vddcr_soc_slope = config->telemetry_vddcr_soc_slope;
65 mcfg->telemetry_vddcr_soc_offset = config->telemetry_vddcr_soc_offset;
68 asmlinkage void car_stage_entry(void)
70 int s3_resume;
72 post_code(0x40);
73 console_init();
75 post_code(0x41);
76 s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3();
78 post_code(0x42);
79 u32 val = cpuid_eax(1);
80 printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
82 post_code(0x43);
83 fsp_memory_init(s3_resume);
84 soc_update_mrc_cache();
86 memmap_stash_early_dram_usage();
88 post_code(0x44);
89 run_ramstage();
91 post_code(0x50); /* Should never see this post code. */