payloads/coreinfo/cpuinfo_module.c

   1 /*
   2  * This file is part of the coreinfo project.
   3  *
   4  * It is derived from the x86info project, which is GPLv2-licensed.
   5  *
   6  * Copyright (C) 2001-2007 Dave Jones <davej@codemonkey.org.uk>
   7  * Copyright (C) 2008 Advanced Micro Devices, Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; version 2 of the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  21  */
  22
  23 #include "coreinfo.h"
  24
  25 #ifdef CONFIG_MODULE_CPUINFO
  26 #include <arch/rdtsc.h>
  27
  28 #define VENDOR_INTEL 0x756e6547
  29 #define VENDOR_AMD   0x68747541
  30 #define VENDOR_CYRIX 0x69727943
  31 #define VENDOR_IDT   0x746e6543
  32 #define VENDOR_GEODE 0x646f6547
  33 #define VENDOR_RISE  0x52697365
  34 #define VENDOR_RISE2 0x65736952
  35 #define VENDOR_SIS   0x20536953
  36
  37 /* CPUID 0x00000001 EDX flags */
  38 static const char *generic_cap_flags[] = {
  39         "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
  40         "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
  41         "pat", "pse36", "psn", "clflsh", NULL, "ds", "acpi", "mmx",
  42         "fxsr", "sse", "sse2", "ss", "ht", "tm", NULL, "pbe"
  43 };
  44
  45 /* CPUID 0x00000001 ECX flags */
  46 static const char *intel_cap_generic_ecx_flags[] = {
  47         "sse3", NULL, NULL, "monitor", "ds-cpl", "vmx", NULL, "est",
  48         "tm2", "ssse3", "cntx-id", NULL, NULL, "cx16", "xTPR", NULL,
  49         NULL, NULL, "dca", NULL, NULL, NULL, NULL, NULL,
  50         NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
  51 };
  52
  53 /* CPUID 0x80000001 EDX flags */
  54 static const char *intel_cap_extended_edx_flags[] = {
  55         NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  56         NULL, NULL, NULL, "SYSCALL", NULL, NULL, NULL, NULL,
  57         NULL, NULL, NULL, NULL, "xd", NULL, NULL, NULL,
  58         NULL, NULL, NULL, NULL, NULL, "em64t", NULL, NULL,
  59 };
  60
  61 /* CPUID 0x80000001 ECX flags */
  62 static const char *intel_cap_extended_ecx_flags[] = {
  63         "lahf_lm", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  64         NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  65         NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  66         NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  67 };
  68
  69 static const char *amd_cap_generic_ecx_flags[] = {
  70         "sse3", NULL, NULL, "mwait", NULL, NULL, NULL, NULL,
  71         NULL, NULL, NULL, NULL, NULL, "cmpxchg16b", NULL, NULL,
  72         NULL, NULL, NULL, NULL, NULL, NULL, NULL, "popcnt",
  73         NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
  74 };
  75
  76 static const char *amd_cap_extended_edx_flags[] = {
  77         "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
  78         "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
  79         "pat", "pse36", NULL, "mp", "nx", NULL, "mmxext", "mmx",
  80         "fxsr", "ffxsr", "page1gb", "rdtscp",
  81         NULL, "lm", "3dnowext", "3dnow"
  82 }; /* "mp" defined for CPUs prior to AMD family 0xf */
  83
  84 static const char *amd_cap_extended_ecx_flags[] = {
  85         "lahf/sahf", "CmpLegacy", "svm", "ExtApicSpace",
  86         "LockMovCr0", "abm", "sse4a", "misalignsse",
  87         "3dnowPref", "osvw", "ibs", NULL, "skinit", "wdt", NULL, NULL,
  88         NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  89         NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
  90 };
  91
  92 static unsigned long vendor;
  93 static unsigned int cpu_khz;
  94
  95 static void decode_flags(WINDOW *win, unsigned long reg, const char **flags,
  96                          int *row)
  97 {
  98         int i;
  99         int lrow = *row;
 100
 101         wmove(win, lrow, 2);
 102
 103         for (i = 0; i < 32; i++) {
 104                 if (flags[i] == NULL)
 105                         continue;
 106
 107                 if (reg & (1 << i))
 108                         wprintw(win, "%s ", flags[i]);
 109
 110                 if (i && (i % 16) == 0) {
 111                         lrow++;
 112                         wmove(win, lrow, 2);
 113                 }
 114         }
 115
 116         *row = lrow;
 117 }
 118
 119 static void get_features(WINDOW *win, int *row)
 120 {
 121         unsigned long eax, ebx, ecx, edx;
 122         int lrow = *row;
 123
 124         wmove(win, lrow++, 1);
 125         wprintw(win, "Features: ");
 126
 127         docpuid(0x00000001, &eax, &ebx, &ecx, &edx);
 128         decode_flags(win, edx, generic_cap_flags, &lrow);
 129
 130         lrow++;
 131
 132         switch (vendor) {
 133         case VENDOR_AMD:
 134                 wmove(win, lrow++, 1);
 135                 wprintw(win, "AMD Extended Flags: ");
 136                 decode_flags(win, ecx, amd_cap_generic_ecx_flags, &lrow);
 137                 docpuid(0x80000001, &eax, &ebx, &ecx, &edx);
 138                 decode_flags(win, edx, amd_cap_extended_edx_flags, &lrow);
 139                 decode_flags(win, ecx, amd_cap_extended_ecx_flags, &lrow);
 140                 break;
 141         case VENDOR_INTEL:
 142                 wmove(win, lrow++, 1);
 143                 wprintw(win, "Intel Extended Flags: ");
 144                 decode_flags(win, ecx, intel_cap_generic_ecx_flags, &lrow);
 145                 docpuid(0x80000001, &eax, &ebx, &ecx, &edx);
 146                 decode_flags(win, edx, intel_cap_extended_edx_flags, &lrow);
 147                 decode_flags(win, ecx, intel_cap_extended_ecx_flags, &lrow);
 148                 break;
 149         }
 150
 151         *row = lrow;
 152 }
 153
 154 static void do_name(WINDOW *win, int row)
 155 {
 156         char name[49], *p;
 157         unsigned long eax, ebx, ecx, edx;
 158         int i, t;
 159
 160         p = name;
 161
 162         for (i = 0x80000002; i <= 0x80000004; i++) {
 163                 docpuid(i, &eax, &ebx, &ecx, &edx);
 164
 165                 if (eax == 0)
 166                         break;
 167
 168                 for (t = 0; t < 4; t++)
 169                         *p++ = eax >> (8 * t);
 170                 for (t = 0; t < 4; t++)
 171                         *p++ = ebx >> (8 * t);
 172                 for (t = 0; t < 4; t++)
 173                         *p++ = ecx >> (8 * t);
 174                 for (t = 0; t < 4; t++)
 175                         *p++ = edx >> (8 * t);
 176         }
 177
 178         mvwprintw(win, row, 1, "Processor: %s", name);
 179 }
 180
 181 static int cpuinfo_module_redraw(WINDOW *win)
 182 {
 183         unsigned long eax, ebx, ecx, edx;
 184         unsigned int brand;
 185         char *vstr;
 186         int row = 2;
 187
 188         print_module_title(win, "CPU Information");
 189
 190         docpuid(0, NULL, &vendor, NULL, NULL);
 191
 192         switch (vendor) {
 193         case VENDOR_INTEL:
 194                 vstr = "Intel";
 195                 break;
 196         case VENDOR_AMD:
 197                 vstr = "AMD";
 198                 break;
 199         case VENDOR_CYRIX:
 200                 vstr = "Cyrix";
 201                 break;
 202         case VENDOR_IDT:
 203                 vstr = "IDT";
 204                 break;
 205         case VENDOR_GEODE:
 206                 vstr = "NatSemi Geode";
 207                 break;
 208         case VENDOR_RISE:
 209         case VENDOR_RISE2:
 210                 vstr = "RISE";
 211                 break;
 212         case VENDOR_SIS:
 213                 vstr = "SiS";
 214                 break;
 215         default:
 216                 vstr = "Unknown";
 217                 break;
 218         }
 219
 220         mvwprintw(win, row++, 1, "Vendor: %s", vstr);
 221
 222         do_name(win, row++);
 223
 224         docpuid(0x00000001, &eax, &ebx, &ecx, &edx);
 225
 226         mvwprintw(win, row++, 1, "Family: %X", (eax >> 8) & 0x0f);
 227         mvwprintw(win, row++, 1, "Model: %X",
 228                   ((eax >> 4) & 0xf) | ((eax >> 16) & 0xf) << 4);
 229
 230         mvwprintw(win, row++, 1, "Stepping: %X", eax & 0xf);
 231
 232         if (vendor == VENDOR_AMD) {
 233                 docpuid(0x80000001, &eax, &ebx, &ecx, &edx);
 234                 brand = ((ebx >> 9) & 0x1f);
 235
 236                 mvwprintw(win, row++, 1, "Brand: %X", brand);
 237         }
 238
 239         if (cpu_khz != 0)
 240                 mvwprintw(win, row++, 1, "CPU Speed: %d Mhz", cpu_khz / 1000);
 241         else
 242                 mvwprintw(win, row++, 1, "CPU Speed: Error");
 243
 244         row++;
 245         get_features(win, &row);
 246
 247         return 0;
 248 }
 249
 250 static unsigned int getticks(void)
 251 {
 252         unsigned long long start, end;
 253
 254         /* Read the number of ticks during the period. */
 255         start = rdtsc();
 256         mdelay(100);
 257         end = rdtsc();
 258
 259         return (unsigned int)((end - start) / 100);
 260 }
 261
 262 static int cpuinfo_module_init(void)
 263 {
 264         cpu_khz = getticks();
 265         return 0;
 266 }
 267
 268 struct coreinfo_module cpuinfo_module = {
 269         .name = "CPU Info",
 270         .init = cpuinfo_module_init,
 271         .redraw = cpuinfo_module_redraw,
 272 };
 273
 274 #else
 275
 276 struct coreinfo_module cpuinfo_module = {
 277 };
 278
 279 #endif