1 /* SPDX-License-Identifier: GPL-2.0-only */
6 #define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
8 /* HFS1[3:0] Current Working State Values */
9 static const char *me_cws_values
[] = {
10 [ME_HFS_CWS_RESET
] = "Reset",
11 [ME_HFS_CWS_INIT
] = "Initializing",
12 [ME_HFS_CWS_REC
] = "Recovery",
13 [ME_HFS_CWS_TEST
] = "Test",
14 [ME_HFS_CWS_DISABLED
] = "Disabled",
15 [ME_HFS_CWS_NORMAL
] = "Normal",
16 [ME_HFS_CWS_WAIT
] = "Platform Disable Wait",
17 [ME_HFS_CWS_TRANS
] = "OP State Transition",
18 [ME_HFS_CWS_INVALID
] = "Invalid CPU Plugged In"
21 /* HFS1[8:6] Current Operation State Values */
22 static const char *me_opstate_values
[] = {
23 [ME_HFS_STATE_PREBOOT
] = "Preboot",
24 [ME_HFS_STATE_M0_UMA
] = "M0 with UMA",
25 [ME_HFS_STATE_M3
] = "M3 without UMA",
26 [ME_HFS_STATE_M0
] = "M0 without UMA",
27 [ME_HFS_STATE_BRINGUP
] = "Bring up",
28 [ME_HFS_STATE_ERROR
] = "M0 without UMA but with error"
31 /* HFS[19:16] Current Operation Mode Values */
32 static const char *me_opmode_values
[] = {
33 [ME_HFS_MODE_NORMAL
] = "Normal",
34 [ME_HFS_MODE_DEBUG
] = "Debug",
35 [ME_HFS_MODE_DIS
] = "Soft Temporary Disable",
36 [ME_HFS_MODE_OVER_JMPR
] = "Security Override via Jumper",
37 [ME_HFS_MODE_OVER_MEI
] = "Security Override via MEI Message"
40 /* HFS[15:12] Error Code Values */
41 static const char *me_error_values
[] = {
42 [ME_HFS_ERROR_NONE
] = "No Error",
43 [ME_HFS_ERROR_UNCAT
] = "Uncategorized Failure",
44 [ME_HFS_ERROR_DISABLED
] = "Disabled",
45 [ME_HFS_ERROR_IMAGE
] = "Image Failure",
46 [ME_HFS_ERROR_DEBUG
] = "Debug Failure"
49 /* GMES[31:28] ME Progress Code */
50 static const char *me_progress_values
[] = {
51 [ME_GMES_PHASE_ROM
] = "ROM Phase",
52 [ME_GMES_PHASE_BUP
] = "BUP Phase",
53 [ME_GMES_PHASE_UKERNEL
] = "uKernel Phase",
54 [ME_GMES_PHASE_POLICY
] = "Policy Module",
55 [ME_GMES_PHASE_MODULE
] = "Module Loading",
56 [ME_GMES_PHASE_UNKNOWN
] = "Unknown",
57 [ME_GMES_PHASE_HOST
] = "Host Communication"
60 /* GMES[27:24] Power Management Event */
61 static const char *me_pmevent_values
[] = {
62 [0x00] = "Clean Moff->Mx wake",
63 [0x01] = "Moff->Mx wake after an error",
64 [0x02] = "Clean global reset",
65 [0x03] = "Global reset after an error",
66 [0x04] = "Clean Intel ME reset",
67 [0x05] = "Intel ME reset due to exception",
68 [0x06] = "Pseudo-global reset",
69 [0x07] = "S0/M0->Sx/M3",
70 [0x08] = "Sx/M3->S0/M0",
71 [0x09] = "Non-power cycle reset",
72 [0x0a] = "Power cycle reset through M3",
73 [0x0b] = "Power cycle reset through Moff",
74 [0x0c] = "Sx/Mx->Sx/Moff"
77 /* Progress Code 0 states */
78 static const char *me_progress_rom_values
[] = {
83 /* Progress Code 1 states */
84 static const char *me_progress_bup_values
[] = {
85 [0x00] = "Initialization starts",
86 [0x01] = "Disable the host wake event",
87 [0x04] = "Flow determination start process",
88 [0x08] = "Error reading/matching the VSCC table in the descriptor",
89 [0x0a] = "Check to see if straps say ME DISABLED",
90 [0x0b] = "Timeout waiting for PWROK",
91 [0x0d] = "Possibly handle BUP manufacturing override strap",
92 [0x11] = "Bringup in M3",
93 [0x12] = "Bringup in M0",
94 [0x13] = "Flow detection error",
95 [0x15] = "M3 clock switching error",
96 [0x18] = "M3 kernel load",
97 [0x1c] = "T34 missing - cannot program ICC",
98 [0x1f] = "Waiting for DID BIOS message",
99 [0x20] = "Waiting for DID BIOS message failure",
100 [0x21] = "DID reported an error",
101 [0x22] = "Enabling UMA",
102 [0x23] = "Enabling UMA error",
103 [0x24] = "Sending DID Ack to BIOS",
104 [0x25] = "Sending DID Ack to BIOS error",
105 [0x26] = "Switching clocks in M0",
106 [0x27] = "Switching clocks in M0 error",
107 [0x28] = "ME in temp disable",
108 [0x32] = "M0 kernel load",
111 /* Progress Code 3 states */
112 static const char *me_progress_policy_values
[] = {
113 [0x00] = "Entery into Policy Module",
114 [0x03] = "Received S3 entry",
115 [0x04] = "Received S4 entry",
116 [0x05] = "Received S5 entry",
117 [0x06] = "Received UPD entry",
118 [0x07] = "Received PCR entry",
119 [0x08] = "Received NPCR entry",
120 [0x09] = "Received host wake",
121 [0x0a] = "Received AC<>DC switch",
122 [0x0b] = "Received DRAM Init Done",
123 [0x0c] = "VSCC Data not found for flash device",
124 [0x0d] = "VSCC Table is not valid",
125 [0x0e] = "Flash Partition Boundary is outside address space",
126 [0x0f] = "ME cannot access the chipset descriptor region",
127 [0x10] = "Required VSCC values for flash parts do not match",
130 void intel_me_status(uint32_t hfs
, uint32_t gmes
)
132 /* Check Current States */
133 printf("ME: FW Partition Table : %s\n",
134 ((hfs
& 0x20) >> 5) ? "BAD" : "OK");
135 printf("ME: Bringup Loader Failure : %s\n",
136 ((hfs
& 0x400) >> 10) ? "YES" : "NO");
137 printf("ME: Firmware Init Complete : %s\n",
138 ((hfs
& 0x200) >> 9) ? "YES" : "NO");
139 printf("ME: Manufacturing Mode : %s\n",
140 ((hfs
& 0x10) >> 4) ? "YES" : "NO");
141 printf("ME: Boot Options Present : %s\n",
142 ((hfs
& 0x1000000) >> 24) ? "YES" : "NO");
143 printf("ME: Update In Progress : %s\n",
144 ((hfs
& 0x800) >> 11) ? "YES" : "NO");
145 printf("ME: Current Working State : %s\n",
146 me_cws_values
[hfs
& 0xf]);
147 printf("ME: Current Operation State : %s\n",
148 me_opstate_values
[(hfs
& 0x1c0) >> 6]);
149 printf("ME: Current Operation Mode : %s\n",
150 me_opmode_values
[(hfs
& 0xf0000) >> 16]);
151 printf("ME: Error Code : %s\n",
152 me_error_values
[(hfs
& 0xf000) >> 12]);
153 printf("ME: Progress Phase : %s\n",
154 me_progress_values
[(gmes
& 0xf0000000) >> 28]);
155 printf("ME: Power Management Event : %s\n",
156 me_pmevent_values
[(gmes
& 0xf000000) >> 24]);
158 printf("ME: Progress Phase State : ");
159 switch ((gmes
& 0xf0000000) >> 28) {
160 case ME_GMES_PHASE_ROM
: /* ROM Phase */
161 printf("%s", me_progress_rom_values
[(gmes
& 0xff0000) >> 16]);
164 case ME_GMES_PHASE_BUP
: /* Bringup Phase */
165 if ((gmes
& 0xff0000) >> 16 < ARRAY_SIZE(me_progress_bup_values
)
166 && me_progress_bup_values
[(gmes
& 0xff0000) >> 16])
168 me_progress_bup_values
[(gmes
& 0xff0000) >> 16]);
170 printf("0x%02x", (gmes
& 0xff0000) >> 16);
173 case ME_GMES_PHASE_POLICY
: /* Policy Module Phase */
174 if ((gmes
& 0xff0000) >> 16 < ARRAY_SIZE(me_progress_policy_values
)
175 && me_progress_policy_values
[(gmes
& 0xff0000) >> 16])
177 me_progress_policy_values
[(gmes
& 0xff0000) >> 16]);
179 printf("0x%02x", (gmes
& 0xff0000) >> 16);
182 case ME_GMES_PHASE_HOST
: /* Host Communication Phase */
183 if (!((gmes
& 0xff0000) >> 16))
184 printf("Host communication established");
186 printf("0x%02x", (gmes
& 0xff0000) >> 16);
190 printf("Unknown 0x%02x", (gmes
& 0xff0000) >> 16);