lint-000-license-headers: Add src/sbom/TAGS to exception list
[coreboot.git] / util / autoport / main.go
blob9b0b43666a61f519509901c4bd8cbab414722750
1 /* This is just an experiment. Full automatic porting
2 is probably not possible but a lot can be automated. */
3 package main
5 import (
6 "bytes"
7 "flag"
8 "fmt"
9 "log"
10 "os"
11 "sort"
12 "strings"
15 type PCIAddr struct {
16 Bus int
17 Dev int
18 Func int
21 type PCIDevData struct {
22 PCIAddr
23 PCIVenID uint16
24 PCIDevID uint16
25 ConfigDump []uint8
28 type PCIDevice interface {
29 Scan(ctx Context, addr PCIDevData)
32 type InteltoolData struct {
33 GPIO map[uint16]uint32
34 RCBA map[uint16]uint32
35 IGD map[uint32]uint32
38 type DMIData struct {
39 Vendor string
40 Model string
41 Version string
42 IsLaptop bool
45 type AzaliaCodec struct {
46 Name string
47 VendorID uint32
48 SubsystemID uint32
49 CodecNo int
50 PinConfig map[int]uint32
53 type DevReader interface {
54 GetPCIList() []PCIDevData
55 GetDMI() DMIData
56 GetInteltool() InteltoolData
57 GetAzaliaCodecs() []AzaliaCodec
58 GetACPI() map[string][]byte
59 GetCPUModel() []uint32
60 GetEC() []byte
61 GetIOPorts() []IOPorts
62 HasPS2() bool
65 type IOPorts struct {
66 Start uint16
67 End uint16
68 Usage string
71 type SouthBridger interface {
72 GetGPIOHeader() string
73 EncodeGPE(int) int
74 DecodeGPE(int) int
75 EnableGPE(int)
76 NeedRouteGPIOManually()
79 var SouthBridge SouthBridger
80 var BootBlockFiles map[string]string = map[string]string{}
81 var ROMStageFiles map[string]string = map[string]string{}
82 var RAMStageFiles map[string]string = map[string]string{}
83 var SMMFiles map[string]string = map[string]string{}
84 var MainboardInit string
85 var MainboardEnable string
86 var MainboardIncludes []string
88 type Context struct {
89 MoboID string
90 KconfigName string
91 Vendor string
92 Model string
93 BaseDirectory string
94 InfoSource DevReader
95 SaneVendor string
98 type IOAPICIRQ struct {
99 APICID int
100 IRQNO [4]int
103 var IOAPICIRQs map[PCIAddr]IOAPICIRQ = map[PCIAddr]IOAPICIRQ{}
104 var KconfigBool map[string]bool = map[string]bool{}
105 var KconfigComment map[string]string = map[string]string{}
106 var KconfigString map[string]string = map[string]string{}
107 var KconfigHex map[string]uint32 = map[string]uint32{}
108 var KconfigInt map[string]int = map[string]int{}
109 var ROMSizeKB = 0
110 var ROMProtocol = ""
111 var FlashROMSupport = ""
113 func GetLE16(inp []byte) uint16 {
114 return uint16(inp[0]) | (uint16(inp[1]) << 8)
117 func FormatHexLE16(inp []byte) string {
118 return fmt.Sprintf("0x%04x", GetLE16(inp))
121 func FormatHex32(u uint32) string {
122 return fmt.Sprintf("0x%08x", u)
125 func FormatHex8(u uint8) string {
126 return fmt.Sprintf("0x%02x", u)
129 func FormatInt32(u uint32) string {
130 return fmt.Sprintf("%d", u)
133 func FormatHexLE32(d []uint8) string {
134 u := uint32(d[0]) | (uint32(d[1]) << 8) | (uint32(d[2]) << 16) | (uint32(d[3]) << 24)
135 return FormatHex32(u)
138 func FormatBool(inp bool) string {
139 if inp {
140 return "1"
141 } else {
142 return "0"
146 func sanitize(inp string) string {
147 result := strings.ToLower(inp)
148 result = strings.Replace(result, " ", "_", -1)
149 result = strings.Replace(result, ",", "_", -1)
150 result = strings.Replace(result, "-", "_", -1)
151 for strings.HasSuffix(result, ".") {
152 result = result[0 : len(result)-1]
154 return result
157 func AddBootBlockFile(Name string, Condition string) {
158 BootBlockFiles[Name] = Condition
161 func AddROMStageFile(Name string, Condition string) {
162 ROMStageFiles[Name] = Condition
165 func AddRAMStageFile(Name string, Condition string) {
166 RAMStageFiles[Name] = Condition
169 func AddSMMFile(Name string, Condition string) {
170 SMMFiles[Name] = Condition
173 func IsIOPortUsedBy(ctx Context, port uint16, name string) bool {
174 for _, io := range ctx.InfoSource.GetIOPorts() {
175 if io.Start <= port && port <= io.End && io.Usage == name {
176 return true
179 return false
182 var FlagOutDir = flag.String("coreboot_dir", ".", "Resulting coreboot directory")
184 func writeMF(mf *os.File, files map[string]string, category string) {
185 keys := []string{}
186 for file, _ := range files {
187 keys = append(keys, file)
190 sort.Strings(keys)
192 for _, file := range keys {
193 condition := files[file]
194 if condition == "" {
195 fmt.Fprintf(mf, "%s-y += %s\n", category, file)
196 } else {
197 fmt.Fprintf(mf, "%s-$(%s) += %s\n", category, condition, file)
202 func Create(ctx Context, name string) *os.File {
203 li := strings.LastIndex(name, "/")
204 if li > 0 {
205 os.MkdirAll(ctx.BaseDirectory+"/"+name[0:li], 0700)
207 mf, err := os.Create(ctx.BaseDirectory + "/" + name)
208 if err != nil {
209 log.Fatal(err)
211 return mf
214 func Add_gpl(f *os.File) {
215 fmt.Fprintln(f, "/* SPDX-License-Identifier: GPL-2.0-only */")
216 fmt.Fprintln(f)
219 func RestorePCI16Simple(f *os.File, pcidev PCIDevData, addr uint16) {
220 fmt.Fprintf(f, " pci_write_config16(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x);\n",
221 pcidev.Bus, pcidev.Dev, pcidev.Func, addr,
222 pcidev.ConfigDump[addr+1],
223 pcidev.ConfigDump[addr])
226 func RestorePCI32Simple(f *os.File, pcidev PCIDevData, addr uint16) {
227 fmt.Fprintf(f, " pci_write_config32(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x%02x%02x);\n",
228 pcidev.Bus, pcidev.Dev, pcidev.Func, addr,
229 pcidev.ConfigDump[addr+3],
230 pcidev.ConfigDump[addr+2],
231 pcidev.ConfigDump[addr+1],
232 pcidev.ConfigDump[addr])
235 func RestoreRCBA32(f *os.File, inteltool InteltoolData, addr uint16) {
236 fmt.Fprintf(f, "\tRCBA32(0x%04x) = 0x%08x;\n", addr, inteltool.RCBA[addr])
239 type PCISlot struct {
240 PCIAddr
241 additionalComment string
242 writeEmpty bool
245 type DevTreeNode struct {
246 Bus int
247 Dev int
248 Func int
249 Disabled bool
250 Registers map[string]string
251 IOs map[uint16]uint16
252 Children []DevTreeNode
253 PCISlots []PCISlot
254 PCIController bool
255 ChildPCIBus int
256 MissingParent string
257 SubVendor uint16
258 SubSystem uint16
259 Chip string
260 Comment string
263 var DevTree DevTreeNode
264 var MissingChildren map[string][]DevTreeNode = map[string][]DevTreeNode{}
265 var unmatchedPCIChips map[PCIAddr]DevTreeNode = map[PCIAddr]DevTreeNode{}
266 var unmatchedPCIDevices map[PCIAddr]DevTreeNode = map[PCIAddr]DevTreeNode{}
268 func Offset(dt *os.File, offset int) {
269 for i := 0; i < offset; i++ {
270 fmt.Fprintf(dt, "\t")
274 func MatchDev(dev *DevTreeNode) {
275 for idx := range dev.Children {
276 MatchDev(&dev.Children[idx])
279 for _, slot := range dev.PCISlots {
280 slotChip, ok := unmatchedPCIChips[slot.PCIAddr]
282 if !ok {
283 continue
286 if slot.additionalComment != "" && slotChip.Comment != "" {
287 slotChip.Comment = slot.additionalComment + " " + slotChip.Comment
288 } else {
289 slotChip.Comment = slot.additionalComment + slotChip.Comment
292 delete(unmatchedPCIChips, slot.PCIAddr)
293 MatchDev(&slotChip)
294 dev.Children = append(dev.Children, slotChip)
297 if dev.PCIController {
298 for slot, slotDev := range unmatchedPCIChips {
299 if slot.Bus == dev.ChildPCIBus {
300 delete(unmatchedPCIChips, slot)
301 MatchDev(&slotDev)
302 dev.Children = append(dev.Children, slotDev)
307 for _, slot := range dev.PCISlots {
308 slotDev, ok := unmatchedPCIDevices[slot.PCIAddr]
309 if !ok {
310 if slot.writeEmpty {
311 dev.Children = append(dev.Children,
312 DevTreeNode{
313 Registers: map[string]string{},
314 Chip: "pci",
315 Bus: slot.Bus,
316 Dev: slot.Dev,
317 Func: slot.Func,
318 Comment: slot.additionalComment,
319 Disabled: true,
323 continue
326 if slot.additionalComment != "" && slotDev.Comment != "" {
327 slotDev.Comment = slot.additionalComment + " " + slotDev.Comment
328 } else {
329 slotDev.Comment = slot.additionalComment + slotDev.Comment
332 MatchDev(&slotDev)
333 dev.Children = append(dev.Children, slotDev)
334 delete(unmatchedPCIDevices, slot.PCIAddr)
337 if dev.MissingParent != "" {
338 for _, child := range MissingChildren[dev.MissingParent] {
339 MatchDev(&child)
340 dev.Children = append(dev.Children, child)
342 delete(MissingChildren, dev.MissingParent)
345 if dev.PCIController {
346 for slot, slotDev := range unmatchedPCIDevices {
347 if slot.Bus == dev.ChildPCIBus {
348 MatchDev(&slotDev)
349 dev.Children = append(dev.Children, slotDev)
350 delete(unmatchedPCIDevices, slot)
356 func writeOn(dt *os.File, dev DevTreeNode) {
357 if dev.Disabled {
358 fmt.Fprintf(dt, "off")
359 } else {
360 fmt.Fprintf(dt, "on")
364 func WriteDev(dt *os.File, offset int, dev DevTreeNode) {
365 Offset(dt, offset)
366 switch dev.Chip {
367 case "cpu_cluster", "lapic", "domain", "ioapic":
368 fmt.Fprintf(dt, "device %s 0x%x ", dev.Chip, dev.Dev)
369 writeOn(dt, dev)
370 case "pci", "pnp":
371 fmt.Fprintf(dt, "device %s %02x.%x ", dev.Chip, dev.Dev, dev.Func)
372 writeOn(dt, dev)
373 case "i2c":
374 fmt.Fprintf(dt, "device %s %02x ", dev.Chip, dev.Dev)
375 writeOn(dt, dev)
376 default:
377 fmt.Fprintf(dt, "chip %s", dev.Chip)
379 if dev.Comment != "" {
380 fmt.Fprintf(dt, " # %s", dev.Comment)
382 fmt.Fprintf(dt, "\n")
383 if dev.Chip == "pci" && dev.SubSystem != 0 && dev.SubVendor != 0 {
384 Offset(dt, offset+1)
385 fmt.Fprintf(dt, "subsystemid 0x%04x 0x%04x\n", dev.SubVendor, dev.SubSystem)
388 ioapic, ok := IOAPICIRQs[PCIAddr{Bus: dev.Bus, Dev: dev.Dev, Func: dev.Func}]
389 if dev.Chip == "pci" && ok {
390 for pin, irq := range ioapic.IRQNO {
391 if irq != 0 {
392 Offset(dt, offset+1)
393 fmt.Fprintf(dt, "ioapic_irq %d INT%c 0x%x\n", ioapic.APICID, 'A'+pin, irq)
398 keys := []string{}
399 for reg, _ := range dev.Registers {
400 keys = append(keys, reg)
403 sort.Strings(keys)
405 for _, reg := range keys {
406 val := dev.Registers[reg]
407 Offset(dt, offset+1)
408 fmt.Fprintf(dt, "register \"%s\" = \"%s\"\n", reg, val)
411 ios := []int{}
412 for reg, _ := range dev.IOs {
413 ios = append(ios, int(reg))
416 sort.Ints(ios)
418 for _, reg := range ios {
419 val := dev.IOs[uint16(reg)]
420 Offset(dt, offset+1)
421 fmt.Fprintf(dt, "io 0x%x = 0x%x\n", reg, val)
424 for _, child := range dev.Children {
425 WriteDev(dt, offset+1, child)
428 Offset(dt, offset)
429 fmt.Fprintf(dt, "end\n")
432 func PutChip(domain string, cur DevTreeNode) {
433 MissingChildren[domain] = append(MissingChildren[domain], cur)
436 func PutPCIChip(addr PCIDevData, cur DevTreeNode) {
437 unmatchedPCIChips[addr.PCIAddr] = cur
440 func PutPCIDevParent(addr PCIDevData, comment string, parent string) {
441 cur := DevTreeNode{
442 Registers: map[string]string{},
443 Chip: "pci",
444 Bus: addr.Bus,
445 Dev: addr.Dev,
446 Func: addr.Func,
447 MissingParent: parent,
448 Comment: comment,
450 if addr.ConfigDump[0xa] == 0x04 && addr.ConfigDump[0xb] == 0x06 {
451 cur.PCIController = true
452 cur.ChildPCIBus = int(addr.ConfigDump[0x19])
454 loopCtr := 0
455 for capPtr := addr.ConfigDump[0x34]; capPtr != 0; capPtr = addr.ConfigDump[capPtr+1] {
456 /* Avoid hangs. There are only 0x100 different possible values for capPtr.
457 If we iterate longer than that, we're in endless loop. */
458 loopCtr++
459 if loopCtr > 0x100 {
460 break
462 if addr.ConfigDump[capPtr] == 0x0d {
463 cur.SubVendor = GetLE16(addr.ConfigDump[capPtr+4 : capPtr+6])
464 cur.SubSystem = GetLE16(addr.ConfigDump[capPtr+6 : capPtr+8])
467 } else {
468 cur.SubVendor = GetLE16(addr.ConfigDump[0x2c:0x2e])
469 cur.SubSystem = GetLE16(addr.ConfigDump[0x2e:0x30])
471 unmatchedPCIDevices[addr.PCIAddr] = cur
474 func PutPCIDev(addr PCIDevData, comment string) {
475 PutPCIDevParent(addr, comment, "")
478 type GenericPCI struct {
479 Comment string
480 Bus0Subdiv string
481 MissingParent string
484 type GenericVGA struct {
485 GenericPCI
488 type DSDTInclude struct {
489 Comment string
490 File string
493 type DSDTDefine struct {
494 Key string
495 Comment string
496 Value string
499 var DSDTIncludes []DSDTInclude
500 var DSDTPCI0Includes []DSDTInclude
501 var DSDTDefines []DSDTDefine
503 func (g GenericPCI) Scan(ctx Context, addr PCIDevData) {
504 PutPCIDevParent(addr, g.Comment, g.MissingParent)
507 var IGDEnabled bool = false
509 func (g GenericVGA) Scan(ctx Context, addr PCIDevData) {
510 KconfigString["VGA_BIOS_ID"] = fmt.Sprintf("%04x,%04x",
511 addr.PCIVenID,
512 addr.PCIDevID)
513 PutPCIDevParent(addr, g.Comment, g.MissingParent)
514 IGDEnabled = true
517 func makeKconfigName(ctx Context) {
518 kn := Create(ctx, "Kconfig.name")
519 defer kn.Close()
521 fmt.Fprintf(kn, "config %s\n\tbool \"%s\"\n", ctx.KconfigName, ctx.Model)
524 func makeComment(name string) string {
525 cmt, ok := KconfigComment[name]
526 if !ok {
527 return ""
529 return " # " + cmt
532 func makeKconfig(ctx Context) {
533 kc := Create(ctx, "Kconfig")
534 defer kc.Close()
536 fmt.Fprintf(kc, "if %s\n\n", ctx.KconfigName)
538 fmt.Fprintf(kc, "config BOARD_SPECIFIC_OPTIONS\n\tdef_bool y\n")
539 keys := []string{}
540 for name, val := range KconfigBool {
541 if val {
542 keys = append(keys, name)
546 sort.Strings(keys)
548 for _, name := range keys {
549 fmt.Fprintf(kc, "\tselect %s%s\n", name, makeComment(name))
552 keys = nil
553 for name, val := range KconfigBool {
554 if !val {
555 keys = append(keys, name)
559 sort.Strings(keys)
561 for _, name := range keys {
562 fmt.Fprintf(kc, `
563 config %s%s
564 bool
565 default n
566 `, name, makeComment(name))
569 keys = nil
570 for name, _ := range KconfigString {
571 keys = append(keys, name)
574 sort.Strings(keys)
576 for _, name := range keys {
577 fmt.Fprintf(kc, `
578 config %s%s
579 string
580 default "%s"
581 `, name, makeComment(name), KconfigString[name])
584 keys = nil
585 for name, _ := range KconfigHex {
586 keys = append(keys, name)
589 sort.Strings(keys)
591 for _, name := range keys {
592 fmt.Fprintf(kc, `
593 config %s%s
595 default 0x%x
596 `, name, makeComment(name), KconfigHex[name])
599 keys = nil
600 for name, _ := range KconfigInt {
601 keys = append(keys, name)
604 sort.Strings(keys)
606 for _, name := range keys {
607 fmt.Fprintf(kc, `
608 config %s%s
610 default %d
611 `, name, makeComment(name), KconfigInt[name])
614 fmt.Fprintf(kc, "endif\n")
617 const MoboDir = "/src/mainboard/"
619 func makeVendor(ctx Context) {
620 vendor := ctx.Vendor
621 vendorSane := ctx.SaneVendor
622 vendorDir := *FlagOutDir + MoboDir + vendorSane
623 vendorUpper := strings.ToUpper(vendorSane)
624 kconfig := vendorDir + "/Kconfig"
625 if _, err := os.Stat(kconfig); os.IsNotExist(err) {
626 f, err := os.Create(kconfig)
627 if err != nil {
628 log.Fatal(err)
630 defer f.Close()
631 f.WriteString(`if VENDOR_` + vendorUpper + `
633 choice
634 prompt "Mainboard model"
636 source "src/mainboard/` + vendorSane + `/*/Kconfig.name"
638 endchoice
640 source "src/mainboard/` + vendorSane + `/*/Kconfig"
642 config MAINBOARD_VENDOR
643 string
644 default "` + vendor + `"
646 endif # VENDOR_` + vendorUpper + "\n")
648 kconfigName := vendorDir + "/Kconfig.name"
649 if _, err := os.Stat(kconfigName); os.IsNotExist(err) {
650 f, err := os.Create(kconfigName)
651 if err != nil {
652 log.Fatal(err)
654 defer f.Close()
655 f.WriteString(`config VENDOR_` + vendorUpper + `
656 bool "` + vendor + `"
662 func GuessECGPE(ctx Context) int {
663 /* FIXME:XX Use iasl -d and/or better parsing */
664 dsdt := ctx.InfoSource.GetACPI()["DSDT"]
665 idx := bytes.Index(dsdt, []byte{0x08, '_', 'G', 'P', 'E', 0x0a}) /* Name (_GPE, byte). */
666 if idx > 0 {
667 return int(dsdt[idx+6])
669 return -1
672 func GuessSPDMap(ctx Context) []uint8 {
673 dmi := ctx.InfoSource.GetDMI()
675 if dmi.Vendor == "LENOVO" {
676 return []uint8{0x50, 0x52, 0x51, 0x53}
678 return []uint8{0x50, 0x51, 0x52, 0x53}
681 func main() {
682 flag.Parse()
684 ctx := Context{}
686 ctx.InfoSource = MakeLogReader()
688 dmi := ctx.InfoSource.GetDMI()
690 ctx.Vendor = dmi.Vendor
692 if dmi.Vendor == "LENOVO" {
693 ctx.Model = dmi.Version
694 } else {
695 ctx.Model = dmi.Model
698 if dmi.IsLaptop {
699 KconfigBool["SYSTEM_TYPE_LAPTOP"] = true
701 ctx.SaneVendor = sanitize(ctx.Vendor)
702 for {
703 last := ctx.SaneVendor
704 for _, suf := range []string{"_inc", "_co", "_corp"} {
705 ctx.SaneVendor = strings.TrimSuffix(ctx.SaneVendor, suf)
707 if last == ctx.SaneVendor {
708 break
711 ctx.MoboID = ctx.SaneVendor + "/" + sanitize(ctx.Model)
712 ctx.KconfigName = "BOARD_" + strings.ToUpper(ctx.SaneVendor+"_"+sanitize(ctx.Model))
713 ctx.BaseDirectory = *FlagOutDir + MoboDir + ctx.MoboID
714 KconfigString["MAINBOARD_DIR"] = ctx.MoboID
715 KconfigString["MAINBOARD_PART_NUMBER"] = ctx.Model
717 os.MkdirAll(ctx.BaseDirectory, 0700)
719 makeVendor(ctx)
721 ScanRoot(ctx)
723 if IGDEnabled {
724 KconfigBool["MAINBOARD_HAS_LIBGFXINIT"] = true
725 KconfigComment["MAINBOARD_HAS_LIBGFXINIT"] = "FIXME: check this"
726 AddRAMStageFile("gma-mainboard.ads", "CONFIG_MAINBOARD_USE_LIBGFXINIT")
729 if len(BootBlockFiles) > 0 || len(ROMStageFiles) > 0 || len(RAMStageFiles) > 0 || len(SMMFiles) > 0 {
730 mf := Create(ctx, "Makefile.inc")
731 defer mf.Close()
732 writeMF(mf, BootBlockFiles, "bootblock")
733 writeMF(mf, ROMStageFiles, "romstage")
734 writeMF(mf, RAMStageFiles, "ramstage")
735 writeMF(mf, SMMFiles, "smm")
738 devtree := Create(ctx, "devicetree.cb")
739 defer devtree.Close()
741 MatchDev(&DevTree)
742 WriteDev(devtree, 0, DevTree)
744 if MainboardInit != "" || MainboardEnable != "" || MainboardIncludes != nil {
745 mainboard := Create(ctx, "mainboard.c")
746 defer mainboard.Close()
747 Add_gpl(mainboard)
748 mainboard.WriteString("#include <device/device.h>\n")
749 for _, include := range MainboardIncludes {
750 mainboard.WriteString("#include <" + include + ">\n")
752 mainboard.WriteString("\n")
753 if MainboardInit != "" {
754 mainboard.WriteString(`static void mainboard_init(struct device *dev)
756 ` + MainboardInit + "}\n\n")
758 if MainboardInit != "" || MainboardEnable != "" {
759 mainboard.WriteString("static void mainboard_enable(struct device *dev)\n{\n")
760 if MainboardInit != "" {
761 mainboard.WriteString("\tdev->ops->init = mainboard_init;\n\n")
763 mainboard.WriteString(MainboardEnable)
764 mainboard.WriteString("}\n\n")
765 mainboard.WriteString(`struct chip_operations mainboard_ops = {
766 .enable_dev = mainboard_enable,
772 bi := Create(ctx, "board_info.txt")
773 defer bi.Close()
775 fixme := ""
777 if dmi.IsLaptop {
778 bi.WriteString("Category: laptop\n")
779 } else {
780 bi.WriteString("Category: desktop\n")
781 fixme += "check category, "
784 missing := "ROM package, ROM socketed"
786 if ROMProtocol != "" {
787 fmt.Fprintf(bi, "ROM protocol: %s\n", ROMProtocol)
788 } else {
789 missing += ", ROM protocol"
792 if FlashROMSupport != "" {
793 fmt.Fprintf(bi, "Flashrom support: %s\n", FlashROMSupport)
794 } else {
795 missing += ", Flashrom support"
798 missing += ", Release year"
800 if fixme != "" {
801 fmt.Fprintf(bi, "FIXME: %s, put %s\n", fixme, missing)
802 } else {
803 fmt.Fprintf(bi, "FIXME: put %s\n", missing)
806 if ROMSizeKB == 0 {
807 KconfigBool["BOARD_ROMSIZE_KB_2048"] = true
808 KconfigComment["BOARD_ROMSIZE_KB_2048"] = "FIXME: correct this"
809 } else {
810 KconfigBool[fmt.Sprintf("BOARD_ROMSIZE_KB_%d", ROMSizeKB)] = true
813 makeKconfig(ctx)
814 makeKconfigName(ctx)
816 dsdt := Create(ctx, "dsdt.asl")
817 defer dsdt.Close()
819 for _, define := range DSDTDefines {
820 if define.Comment != "" {
821 fmt.Fprintf(dsdt, "\t/* %s. */\n", define.Comment)
823 dsdt.WriteString("#define " + define.Key + " " + define.Value + "\n")
826 Add_gpl(dsdt)
827 dsdt.WriteString(
829 #include <acpi/acpi.h>
831 DefinitionBlock(
832 "dsdt.aml",
833 "DSDT",
834 ACPI_DSDT_REV_2,
835 OEM_ID,
836 ACPI_TABLE_CREATOR,
837 0x20141018 /* OEM revision */
840 #include <acpi/dsdt_top.asl>
841 #include "acpi/platform.asl"
844 for _, x := range DSDTIncludes {
845 if x.Comment != "" {
846 fmt.Fprintf(dsdt, "\t/* %s. */\n", x.Comment)
848 fmt.Fprintf(dsdt, "\t#include <%s>\n", x.File)
851 dsdt.WriteString(`
852 Device (\_SB.PCI0)
855 for _, x := range DSDTPCI0Includes {
856 if x.Comment != "" {
857 fmt.Fprintf(dsdt, "\t/* %s. */\n", x.Comment)
859 fmt.Fprintf(dsdt, "\t\t#include <%s>\n", x.File)
861 dsdt.WriteString(
866 if IGDEnabled {
867 gma := Create(ctx, "gma-mainboard.ads")
868 defer gma.Close()
870 gma.WriteString(`-- SPDX-License-Identifier: GPL-2.0-or-later
872 with HW.GFX.GMA;
873 with HW.GFX.GMA.Display_Probing;
875 use HW.GFX.GMA;
876 use HW.GFX.GMA.Display_Probing;
878 private package GMA.Mainboard is
880 -- FIXME: check this
881 ports : constant Port_List :=
882 (DP1,
883 DP2,
884 DP3,
885 HDMI1,
886 HDMI2,
887 HDMI3,
888 Analog,
889 LVDS,
890 eDP);
892 end GMA.Mainboard;