src/northbridge/intel/gm45/northbridge.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <cbmem.h>
   4 #include <commonlib/helpers.h>
   5 #include <console/console.h>
   6 #include <device/pci_def.h>
   7 #include <device/pci_ops.h>
   8 #include <stdint.h>
   9 #include <device/device.h>
  10 #include <boot/tables.h>
  11 #include <acpi/acpi.h>
  12 #include <cpu/intel/smm_reloc.h>
  13
  14 #include "chip.h"
  15 #include "gm45.h"
  16
  17 /* Reserve segments A and B:
  18  *
  19  * 0xa0000 - 0xbffff: legacy VGA
  20  */
  21 static const int legacy_hole_base_k = 0xa0000 / 1024;
  22 static const int legacy_hole_size_k = 128;
  23
  24 static int decode_pcie_bar(u32 *const base, u32 *const len)
  25 {
  26         *base = 0;
  27         *len = 0;
  28
  29         struct device *dev = pcidev_on_root(0, 0);
  30         if (!dev)
  31                 return 0;
  32
  33         const u32 pciexbar_reg = pci_read_config32(dev, D0F0_PCIEXBAR_LO);
  34
  35         if (!(pciexbar_reg & (1 << 0)))
  36                 return 0;
  37
  38         switch ((pciexbar_reg >> 1) & 3) {
  39         case 0: /* 256MB */
  40                 *base = pciexbar_reg & (0x0f << 28);
  41                 *len = 256 * MiB;
  42                 return 1;
  43         case 1: /* 128M */
  44                 *base = pciexbar_reg & (0x1f << 27);
  45                 *len = 128 * MiB;
  46                 return 1;
  47         case 2: /* 64M */
  48                 *base = pciexbar_reg & (0x3f << 26);
  49                 *len = 64 * MiB;
  50                 return 1;
  51         }
  52
  53         return 0;
  54 }
  55
  56 static void mch_domain_read_resources(struct device *dev)
  57 {
  58         u64 tom, touud;
  59         u32 tomk, tolud, uma_sizek = 0, delta_cbmem;
  60         u32 pcie_config_base, pcie_config_size;
  61
  62         /* Total Memory 2GB example:
  63          *
  64          *  00000000  0000MB-2014MB  2014MB  RAM     (writeback)
  65          *  7de00000  2014MB-2016MB     2MB  GFX GTT (uncached)
  66          *  7e000000  2016MB-2048MB    32MB  GFX UMA (uncached)
  67          *  80000000   2048MB TOLUD
  68          *  80000000   2048MB TOM
  69          *
  70          * Total Memory 4GB example:
  71          *
  72          *  00000000  0000MB-3038MB  3038MB  RAM     (writeback)
  73          *  bde00000  3038MB-3040MB     2MB  GFX GTT (uncached)
  74          *  be000000  3040MB-3072MB    32MB  GFX UMA (uncached)
  75          *  be000000   3072MB TOLUD
  76          * 100000000   4096MB TOM
  77          * 100000000  4096MB-5120MB  1024MB  RAM     (writeback)
  78          * 140000000   5120MB TOUUD
  79          */
  80
  81         pci_domain_read_resources(dev);
  82
  83         struct device *mch = pcidev_on_root(0, 0);
  84
  85         /* Top of Upper Usable DRAM, including remap */
  86         touud = pci_read_config16(mch, D0F0_TOUUD);
  87         touud <<= 20;
  88
  89         /* Top of Lower Usable DRAM */
  90         tolud = pci_read_config16(mch, D0F0_TOLUD) & 0xfff0;
  91         tolud <<= 16;
  92
  93         /* Top of Memory - does not account for any UMA */
  94         tom = pci_read_config16(mch, D0F0_TOM) & 0x1ff;
  95         tom <<= 27;
  96
  97         printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n",
  98                touud, tolud, tom);
  99
 100         tomk = tolud >> 10;
 101
 102         /* Graphics memory comes next */
 103         const u16 ggc = pci_read_config16(mch, D0F0_GGC);
 104         if (!(ggc & 2)) {
 105                 printk(BIOS_DEBUG, "IGD decoded, subtracting ");
 106
 107                 /* Graphics memory */
 108                 const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf);
 109                 printk(BIOS_DEBUG, "%uM UMA, ", gms_sizek >> 10);
 110                 tomk -= gms_sizek;
 111
 112                 /* GTT Graphics Stolen Memory Size (GGMS) */
 113                 const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf);
 114                 printk(BIOS_DEBUG, "%uM GTT", gsm_sizek >> 10);
 115                 tomk -= gsm_sizek;
 116
 117                 uma_sizek = gms_sizek + gsm_sizek;
 118         }
 119         const u8 esmramc = pci_read_config8(mch, D0F0_ESMRAMC);
 120         const u32 tseg_sizek = decode_tseg_size(esmramc);
 121         printk(BIOS_DEBUG, " and %uM TSEG\n", tseg_sizek >> 10);
 122         tomk -= tseg_sizek;
 123         uma_sizek += tseg_sizek;
 124
 125         /* cbmem_top can be shifted downwards due to alignment.
 126            Mark the region between cbmem_top and tomk as unusable */
 127         delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10);
 128         tomk -= delta_cbmem;
 129         uma_sizek += delta_cbmem;
 130
 131         printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n",
 132                delta_cbmem);
 133
 134         printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10);
 135
 136         /* Report the memory regions */
 137         ram_resource(dev, 3, 0, legacy_hole_base_k);
 138         ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k,
 139                      (tomk - (legacy_hole_base_k + legacy_hole_size_k)));
 140
 141         /*
 142          * If >= 4GB installed then memory from TOLUD to 4GB
 143          * is remapped above TOM, TOUUD will account for both
 144          */
 145         touud >>= 10; /* Convert to KB */
 146         if (touud > 4096 * 1024) {
 147                 ram_resource(dev, 5, 4096 * 1024, touud - (4096 * 1024));
 148                 printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",
 149                        (touud >> 10) - 4096);
 150         }
 151
 152         printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx "
 153                "size=0x%llx\n", ((u64)tomk) << 10, ((u64)uma_sizek) << 10);
 154         /* Don't use uma_resource() as our UMA touches the PCI hole. */
 155         fixed_mem_resource(dev, 6, tomk, uma_sizek, IORESOURCE_RESERVE);
 156
 157         if (decode_pcie_bar(&pcie_config_base, &pcie_config_size)) {
 158                 printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
 159                        "size=0x%x\n", pcie_config_base, pcie_config_size);
 160                 fixed_mem_resource(dev, 7, pcie_config_base >> 10,
 161                         pcie_config_size >> 10, IORESOURCE_RESERVE);
 162         }
 163 }
 164
 165 static void mch_domain_set_resources(struct device *dev)
 166 {
 167         struct resource *resource;
 168         int i;
 169
 170         for (i = 3; i < 8; ++i) {
 171                 /* Report read resources. */
 172                 resource = probe_resource(dev, i);
 173                 if (resource)
 174                         report_resource_stored(dev, resource, "");
 175         }
 176
 177         assign_resources(dev->link_list);
 178 }
 179
 180 static void mch_domain_init(struct device *dev)
 181 {
 182         struct device *mch = pcidev_on_root(0, 0);
 183
 184         /* Enable SERR */
 185         pci_or_config16(mch, PCI_COMMAND, PCI_COMMAND_SERR);
 186 }
 187
 188 static const char *northbridge_acpi_name(const struct device *dev)
 189 {
 190         if (dev->path.type == DEVICE_PATH_DOMAIN)
 191                 return "PCI0";
 192
 193         if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0)
 194                 return NULL;
 195
 196         switch (dev->path.pci.devfn) {
 197         case PCI_DEVFN(0, 0):
 198                 return "MCHC";
 199         }
 200
 201         return NULL;
 202 }
 203
 204 void northbridge_write_smram(u8 smram)
 205 {
 206         struct device *dev = pcidev_on_root(0, 0);
 207
 208         if (dev == NULL)
 209                 die("could not find pci 00:00.0!\n");
 210
 211         pci_write_config8(dev, D0F0_SMRAM, smram);
 212 }
 213
 214 static struct device_operations pci_domain_ops = {
 215         .read_resources   = mch_domain_read_resources,
 216         .set_resources    = mch_domain_set_resources,
 217         .init             = mch_domain_init,
 218         .scan_bus         = pci_domain_scan_bus,
 219         .write_acpi_tables = northbridge_write_acpi_tables,
 220         .acpi_fill_ssdt   = generate_cpu_entries,
 221         .acpi_name        = northbridge_acpi_name,
 222 };
 223
 224 static struct device_operations cpu_bus_ops = {
 225         .read_resources   = noop_read_resources,
 226         .set_resources    = noop_set_resources,
 227         .init             = mp_cpu_bus_init,
 228 };
 229
 230 static void enable_dev(struct device *dev)
 231 {
 232         /* Set the operations if it is a special bus type */
 233         if (dev->path.type == DEVICE_PATH_DOMAIN) {
 234                 dev->ops = &pci_domain_ops;
 235         } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
 236                 dev->ops = &cpu_bus_ops;
 237         }
 238 }
 239
 240 static void gm45_init(void *const chip_info)
 241 {
 242         int dev, fn, bit_base;
 243
 244         struct device *const d0f0 = pcidev_on_root(0x0, 0);
 245
 246         /* Hide internal functions based on devicetree info. */
 247         for (dev = 3; dev > 0; --dev) {
 248                 switch (dev) {
 249                 case 3: /* ME */
 250                         fn = 3;
 251                         bit_base = 6;
 252                         break;
 253                 case 2: /* IGD */
 254                         fn = 1;
 255                         bit_base = 3;
 256                         break;
 257                 case 1: /* PEG */
 258                         fn = 0;
 259                         bit_base = 1;
 260                         break;
 261                 }
 262                 for (; fn >= 0; --fn) {
 263                         const struct device *const d = pcidev_on_root(dev, fn);
 264                         if (!d || d->enabled)
 265                                 continue;
 266                         /* FIXME: Using bitwise ops changes the binary */
 267                         pci_write_config32(d0f0, D0F0_DEVEN,
 268                                 pci_read_config32(d0f0, D0F0_DEVEN) & ~(1 << (bit_base + fn)));
 269                 }
 270         }
 271
 272         const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN);
 273         if (!(deven & (0xf << 6)))
 274                 pci_write_config32(d0f0, D0F0_DEVEN, deven & ~(1 << 14));
 275 }
 276
 277 struct chip_operations northbridge_intel_gm45_ops = {
 278         CHIP_NAME("Intel GM45 Northbridge")
 279         .enable_dev = enable_dev,
 280         .init = gm45_init,
 281 };