2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
5 ## Copyright (C) 2009-2010 coresystems GmbH
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; version 2 of the License.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
17 mainmenu "coreboot configuration"
26 string "Local version string"
28 Append an extra string to the end of the coreboot version.
30 This can be useful if, for instance, you want to append the
31 respective board's hostname or some other identifying string to
32 the coreboot version number, so that you can easily distinguish
33 boot logs of different boards from each other.
35 config CONFIGURABLE_CBFS_PREFIX
38 Select this to prompt to use to configure the prefix for cbfs files.
41 string "CBFS prefix to use" if CONFIGURABLE_CBFS_PREFIX
44 Select the prefix to all files put into the image. It's "fallback"
45 by default, "normal" is a common alternative.
48 prompt "Compiler to use"
51 This option allows you to select the compiler used for building
53 You must build the coreboot crosscompiler for the board that you
56 To build all the GCC crosscompilers (takes a LONG time), run:
59 For help on individual architectures, run the command:
65 Use the GNU Compiler Collection (GCC) to build coreboot.
67 For details see http://gcc.gnu.org.
69 config COMPILER_LLVM_CLANG
70 bool "LLVM/clang (TESTING ONLY - Not currently working)"
72 Use LLVM/clang to build coreboot. To use this, you must build the
73 coreboot version of the clang compiler. Run the command
75 Note that this option is not currently working correctly and should
76 really only be selected if you're trying to work on getting clang
79 For details see http://clang.llvm.org.
84 bool "Allow building with any toolchain"
87 Many toolchains break when building coreboot since it uses quite
88 unusual linker features. Unless developers explicitely request it,
89 we'll have to assume that they use their distro compiler by mistake.
90 Make sure that using patched compilers is a conscious decision.
93 bool "Use ccache to speed up (re)compilation"
96 Enables the use of ccache for faster builds.
98 Requires the ccache utility in your system $PATH.
100 For details see https://ccache.samba.org.
103 bool "Generate flashmap descriptor parser using flex and bison"
106 Enable this option if you are working on the flashmap descriptor
107 parser and made changes to fmd_scanner.l or fmd_parser.y.
109 Otherwise, say N to use the provided pregenerated scanner/parser.
111 config UTIL_GENPARSER
112 bool "Generate SCONFIG & BINCFG parser using flex and bison"
115 Enable this option if you are working on the sconfig device tree
116 parser or bincfg and made changes to the .l or .y files.
118 Otherwise, say N to use the provided pregenerated scanner/parser.
120 config USE_OPTION_TABLE
121 bool "Use CMOS for configuration values"
122 depends on HAVE_OPTION_TABLE
124 Enable this option if coreboot shall read options from the "CMOS"
125 NVRAM instead of using hard-coded values.
127 config STATIC_OPTION_TABLE
128 bool "Load default configuration values into CMOS on each boot"
129 depends on USE_OPTION_TABLE
131 Enable this option to reset "CMOS" NVRAM values to default on
132 every boot. Use this if you want the NVRAM configuration to
133 never be modified from its default values.
135 config COMPRESS_RAMSTAGE
136 bool "Compress ramstage with LZMA"
137 depends on HAVE_RAMSTAGE
138 # Default value set at the end of the file
140 Compress ramstage to save memory in the flash image. Note
141 that decompression might slow down booting if the boot flash
142 is connected through a slow link (i.e. SPI).
144 config COMPRESS_PRERAM_STAGES
145 bool "Compress romstage and verstage with LZ4"
146 depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE)
147 # Default value set at the end of the file
149 Compress romstage and (if it exists) verstage with LZ4 to save flash
150 space and speed up boot, since the time for reading the image from SPI
151 (and in the vboot case verifying it) is usually much greater than the
152 time spent decompressing. Doesn't work for XIP stages (assume all
153 ARCH_X86 for now) for obvious reasons.
155 config COMPRESS_BOOTBLOCK
157 depends on HAVE_BOOTBLOCK
159 This option can be used to compress the bootblock with LZ4 and attach
160 a small self-decompression stub to its front. This can drastically
161 reduce boot time on platforms where the bootblock is loaded over a
162 very slow connection and bootblock size trumps all other factors for
163 speed. Since using this option usually requires changes to the
164 SoC memlayout and possibly extra support code, it should not be
165 user-selectable. (There's no real point in offering this to the user
166 anyway... if it works and saves boot time, you would always want it.)
168 config INCLUDE_CONFIG_FILE
169 bool "Include the coreboot .config file into the ROM image"
170 # Default value set at the end of the file
172 Include the .config file that was used to compile coreboot
173 in the (CBFS) ROM image. This is useful if you want to know which
174 options were used to build a specific coreboot.rom image.
176 Saying Y here will increase the image size by 2-3KB.
178 You can use the following command to easily list the options:
180 grep -a CONFIG_ coreboot.rom
182 Alternatively, you can also use cbfstool to print the image
183 contents (including the raw 'config' item we're looking for).
187 $ cbfstool coreboot.rom print
188 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
192 Name Offset Type Size
193 cmos_layout.bin 0x0 cmos layout 1159
194 fallback/romstage 0x4c0 stage 339756
195 fallback/ramstage 0x53440 stage 186664
196 fallback/payload 0x80dc0 payload 51526
197 config 0x8d740 raw 3324
198 (empty) 0x8e480 null 3610440
200 config COLLECT_TIMESTAMPS
201 bool "Create a table of timestamps collected during boot"
202 default y if ARCH_X86
204 Make coreboot create a table of timer-ID/timer-value pairs to
205 allow measuring time spent at different phases of the boot process.
207 config TIMESTAMPS_ON_CONSOLE
208 bool "Print the timestamp values on the console"
210 depends on COLLECT_TIMESTAMPS
212 Print the timestamps to the debug console if enabled at level spew.
215 bool "Allow use of binary-only repository"
217 This draws in the blobs repository, which contains binary files that
218 might be required for some chipsets or boards.
219 This flag ensures that a "Free" option remains available for users.
222 bool "Code coverage support"
223 depends on COMPILER_GCC
225 Add code coverage support for coreboot. This will store code
226 coverage information in CBMEM for extraction from user space.
230 bool "Undefined behavior sanitizer support"
233 Instrument the code with checks for undefined behavior. If unsure,
234 say N because it adds a small performance penalty and may abort
235 on code that happens to work in spite of the UB.
237 config NO_RELOCATABLE_RAMSTAGE
239 default n if ARCH_X86
242 config RELOCATABLE_RAMSTAGE
244 default !NO_RELOCATABLE_RAMSTAGE
245 select RELOCATABLE_MODULES
247 The reloctable ramstage support allows for the ramstage to be built
248 as a relocatable module. The stage loader can identify a place
249 out of the OS way so that copying memory is unnecessary during an S3
250 wake. When selecting this option the romstage is responsible for
251 determing a stack location to use for loading the ramstage.
253 config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
254 depends on RELOCATABLE_RAMSTAGE
257 The relocated ramstage is saved in an area specified by the
258 by the board and/or chipset.
261 bool "Update existing coreboot.rom image"
263 If this option is enabled, no new coreboot.rom file
264 is created. Instead it is expected that there already
265 is a suitable file for further processing.
266 The bootblock will not be modified.
268 If unsure, select 'N'
270 config BOOTSPLASH_IMAGE
271 bool "Add a bootsplash image"
273 Select this option if you have a bootsplash image that you would
274 like to add to your ROM.
276 This will only add the image to the ROM. To actually run it check
277 options under 'Display' section.
279 config BOOTSPLASH_FILE
280 string "Bootsplash path and filename"
281 depends on BOOTSPLASH_IMAGE
282 # Default value set at the end of the file
284 The path and filename of the file to use as graphical bootsplash
285 screen. The file format has to be jpg.
287 config HAVE_RAMPAYLOAD
291 bool "Enable coreboot flow without executing ramstage"
292 default y if ARCH_X86
293 depends on HAVE_RAMPAYLOAD
295 If this option is enabled, coreboot flow will skip ramstage
296 loading and execution of ramstage to load payload.
298 Instead it is expected to load payload from postcar stage itself.
300 In this flow coreboot will perform basic x86 initialization
301 (DRAM resource allocation), MTRR programming,
302 Skip PCI enumeration logic and only allocate BAR for fixed devices
303 (bootable devices, TPM over GSPI).
309 source "src/mainboard/Kconfig"
313 default "devicetree.cb"
315 This symbol allows mainboards to select a different file under their
316 mainboard directory for the devicetree.cb file. This allows the board
317 variants that need different devicetrees to be in the same directory.
319 Examples: "devicetree.variant.cb"
320 "variant/devicetree.cb"
322 config OVERRIDE_DEVICETREE
326 This symbol allows variants to provide an override devicetree file to
327 override the registers and/or add new devices on top of the ones
328 provided by baseboard devicetree using CONFIG_DEVICETREE.
330 Examples: "devicetree.variant-override.cb"
331 "variant/devicetree-override.cb"
334 hex "Size of CBFS filesystem in ROM"
335 # Default value set at the end of the file
337 This is the part of the ROM actually managed by CBFS, located at the
338 end of the ROM (passed through cbfstool -o) on x86 and at at the start
339 of the ROM (passed through cbfstool -s) everywhere else. It defaults
340 to span the whole ROM on all but Intel systems that use an Intel Firmware
341 Descriptor. It can be overridden to make coreboot live alongside other
342 components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
346 string "fmap description file in fmd format"
347 default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
350 The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
351 but in some cases more complex setups are required.
352 When an fmd is specified, it overrides the default format.
356 # load site-local kconfig to allow user specific defaults and overrides
357 source "site-local/Kconfig"
359 config SYSTEM_TYPE_LAPTOP
363 config SYSTEM_TYPE_TABLET
367 config SYSTEM_TYPE_DETACHABLE
371 config SYSTEM_TYPE_CONVERTIBLE
375 config CBFS_AUTOGEN_ATTRIBUTES
379 If this option is selected, every file in cbfs which has a constraint
380 regarding position or alignment will get an additional file attribute
381 which describes this constraint.
386 source "src/soc/*/Kconfig"
388 source "src/cpu/Kconfig"
389 comment "Northbridge"
390 source "src/northbridge/*/*/Kconfig"
391 comment "Southbridge"
392 source "src/southbridge/*/*/Kconfig"
394 source "src/superio/*/*/Kconfig"
395 comment "Embedded Controllers"
396 source "src/ec/acpi/Kconfig"
397 source "src/ec/*/*/Kconfig"
399 source "src/southbridge/intel/common/firmware/Kconfig"
400 source "src/vendorcode/*/Kconfig"
402 source "src/arch/*/Kconfig"
406 source "src/device/Kconfig"
408 menu "Generic Drivers"
409 source "src/drivers/*/Kconfig"
410 source "src/drivers/*/*/Kconfig"
411 source "src/commonlib/storage/Kconfig"
416 source "src/security/Kconfig"
420 source "src/acpi/Kconfig"
422 # This option is for the current boards/chipsets where SPI flash
423 # is not the boot device. Currently nearly all boards/chipsets assume
424 # SPI flash is the boot device.
425 config BOOT_DEVICE_NOT_SPI_FLASH
429 config BOOT_DEVICE_SPI_FLASH
431 default y if !BOOT_DEVICE_NOT_SPI_FLASH
434 config BOOT_DEVICE_MEMORY_MAPPED
436 default y if ARCH_X86 && BOOT_DEVICE_SPI_FLASH
439 Inform system if SPI is memory-mapped or not.
441 config BOOT_DEVICE_SUPPORTS_WRITES
445 Indicate that the platform has writable boot device
454 default 0x100000 if FLATTENED_DEVICE_TREE
459 default 0x1000 if ARCH_X86
466 source "src/console/Kconfig"
468 config HAVE_ACPI_RESUME
472 config ACPI_HUGE_LOWMEM_BACKUP
476 On S3 resume path, backup low memory from RAMBASE..RAMTOP in CBMEM.
478 config RESUME_PATH_SAME_AS_BOOT
480 default y if ARCH_X86
481 depends on HAVE_ACPI_RESUME
483 This option indicates that when a system resumes it takes the
484 same path as a regular boot. e.g. an x86 system runs from the
485 reset vector at 0xfffffff0 on both resume and warm/cold boot.
487 config HAVE_ROMSTAGE_CONSOLE_SPINLOCK
491 config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
495 This should be enabled on certain plaforms, such as the AMD
496 SR565x, that cannot handle concurrent CBFS accesses from
497 multiple APs during early startup.
499 config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK
503 config NO_MONOTONIC_TIMER
506 config HAVE_MONOTONIC_TIMER
508 depends on !NO_MONOTONIC_TIMER
511 The board/chipset provides a monotonic timer.
513 config GENERIC_UDELAY
515 depends on HAVE_MONOTONIC_TIMER
516 default y if !ARCH_X86
518 The board/chipset uses a generic udelay function utilizing the
523 depends on HAVE_MONOTONIC_TIMER
525 Provide a timer queue for performing time-based callbacks.
527 config COOP_MULTITASKING
529 depends on TIMER_QUEUE && ARCH_X86
531 Cooperative multitasking allows callbacks to be multiplexed on the
532 main thread of ramstage. With this enabled it allows for multiple
533 execution paths to take place when they have udelay() calls within
539 depends on COOP_MULTITASKING
541 How many execution threads to cooperatively multitask with.
543 config HAVE_OPTION_TABLE
547 This variable specifies whether a given board has a cmos.layout
548 file containing NVRAM/CMOS bit definitions.
549 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
551 config PCI_IO_CFG_EXT
559 config USE_WATCHDOG_ON_BOOT
567 Enable Unified Memory Architecture for graphics.
569 config HAVE_ACPI_TABLES
572 This variable specifies whether a given board has ACPI table support.
573 It is usually set in mainboard/*/Kconfig.
578 This variable specifies whether a given board has MP table support.
579 It is usually set in mainboard/*/Kconfig.
580 Whether or not the MP table is actually generated by coreboot
581 is configurable by the user via GENERATE_MP_TABLE.
583 config HAVE_PIRQ_TABLE
586 This variable specifies whether a given board has PIRQ table support.
587 It is usually set in mainboard/*/Kconfig.
588 Whether or not the PIRQ table is actually generated by coreboot
589 is configurable by the user via GENERATE_PIRQ_TABLE.
599 Build support for NHLT (non HD Audio) ACPI table generation.
603 depends on HAVE_ACPI_TABLES
605 Build an ACPI Boot Error Record Table.
607 #These Options are here to avoid "undefined" warnings.
608 #The actual selection and help texts are in the following menu.
612 config GENERATE_MP_TABLE
613 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
615 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
617 Generate an MP table (conforming to the Intel MultiProcessor
618 specification 1.4) for this board.
622 config GENERATE_PIRQ_TABLE
623 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
625 default HAVE_PIRQ_TABLE
627 Generate a PIRQ table for this board.
631 config GENERATE_SMBIOS_TABLES
633 bool "Generate SMBIOS tables"
636 Generate SMBIOS tables for this board.
640 config SMBIOS_PROVIDED_BY_MOBO
644 config MAINBOARD_SERIAL_NUMBER
645 prompt "SMBIOS Serial Number" if !SMBIOS_PROVIDED_BY_MOBO
647 depends on GENERATE_SMBIOS_TABLES
650 The Serial Number to store in SMBIOS structures.
652 config MAINBOARD_VERSION
653 prompt "SMBIOS Version Number" if !SMBIOS_PROVIDED_BY_MOBO
655 depends on GENERATE_SMBIOS_TABLES
658 The Version Number to store in SMBIOS structures.
660 config MAINBOARD_SMBIOS_MANUFACTURER
661 prompt "SMBIOS Manufacturer" if !SMBIOS_PROVIDED_BY_MOBO
663 depends on GENERATE_SMBIOS_TABLES
664 default MAINBOARD_VENDOR
666 Override the default Manufacturer stored in SMBIOS structures.
668 config MAINBOARD_SMBIOS_PRODUCT_NAME
669 prompt "SMBIOS Product name" if !SMBIOS_PROVIDED_BY_MOBO
671 depends on GENERATE_SMBIOS_TABLES
672 default MAINBOARD_PART_NUMBER
674 Override the default Product name stored in SMBIOS structures.
676 config SMBIOS_ENCLOSURE_TYPE
678 depends on GENERATE_SMBIOS_TABLES
679 default 0x09 if SYSTEM_TYPE_LAPTOP
680 default 0x1e if SYSTEM_TYPE_TABLET
681 default 0x1f if SYSTEM_TYPE_CONVERTIBLE
682 default 0x20 if SYSTEM_TYPE_DETACHABLE
685 System Enclosure or Chassis Types as defined in SMBIOS specification.
686 The default value is SMBIOS_ENCLOSURE_DESKTOP (0x03) but laptop,
687 convertible, or tablet enclosure will be used if the appropriate
688 system type is selected.
692 source "payloads/Kconfig"
696 comment "CPU Debug Settings"
697 source "src/cpu/*/Kconfig.debug"
699 comment "General Debug Settings"
701 # TODO: Better help text and detailed instructions.
703 bool "GDB debugging support"
705 depends on CONSOLE_SERIAL
707 If enabled, you will be able to set breakpoints for gdb debugging.
708 See src/arch/x86/lib/c_start.S for details.
711 bool "Wait for a GDB connection in the ramstage"
715 If enabled, coreboot will wait for a GDB connection in the ramstage.
719 bool "Halt when hitting a BUG() or assertion error"
722 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
724 config HAVE_DEBUG_GPIO
728 bool "Output verbose GPIO debug messages"
729 depends on HAVE_DEBUG_GPIO
732 bool "Output verbose CBFS debug messages"
735 This option enables additional CBFS related debug messages.
737 config HAVE_DEBUG_RAM_SETUP
740 config DEBUG_RAM_SETUP
741 bool "Output verbose RAM init debug messages"
743 depends on HAVE_DEBUG_RAM_SETUP
745 This option enables additional RAM init related debug messages.
746 It is recommended to enable this when debugging issues on your
747 board which might be RAM init related.
749 Note: This option will increase the size of the coreboot image.
754 bool "Check PIRQ table consistency"
756 depends on GENERATE_PIRQ_TABLE
760 config HAVE_DEBUG_SMBUS
764 bool "Output verbose SMBus debug messages"
766 depends on HAVE_DEBUG_SMBUS
768 This option enables additional SMBus (and SPD) debug messages.
770 Note: This option will increase the size of the coreboot image.
775 bool "Output verbose SMI debug messages"
777 depends on HAVE_SMI_HANDLER
778 select SPI_FLASH_SMM if SPI_CONSOLE || CONSOLE_SPI_FLASH
780 This option enables additional SMI related debug messages.
782 Note: This option will increase the size of the coreboot image.
786 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
787 # printk(BIOS_DEBUG, ...) calls.
789 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
793 This option enables additional malloc related debug messages.
795 Note: This option will increase the size of the coreboot image.
799 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
800 # printk(BIOS_DEBUG, ...) calls.
802 prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
806 This option enables additional ACPI related debug messages.
808 Note: This option will slightly increase the size of the coreboot image.
812 config DEBUG_CONSOLE_INIT
813 bool "Debug console initialisation code"
816 With this option printk()'s are attempted before console hardware
817 initialisation has been completed. Your mileage may vary.
819 Typically you will need to modify source in console_hw_init() such
820 that a working console appears before the one you want to debug.
824 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
825 # printk(BIOS_DEBUG, ...) calls.
826 config REALMODE_DEBUG
827 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
830 depends on PCI_OPTION_ROM_RUN_REALMODE
832 This option enables additional x86emu related debug messages.
834 Note: This option will increase the time to emulate a ROM.
839 bool "Output verbose x86emu debug messages"
841 depends on PCI_OPTION_ROM_RUN_YABEL
843 This option enables additional x86emu related debug messages.
845 Note: This option will increase the size of the coreboot image.
849 config X86EMU_DEBUG_JMP
850 bool "Trace JMP/RETF"
852 depends on X86EMU_DEBUG
854 Print information about JMP and RETF opcodes from x86emu.
856 Note: This option will increase the size of the coreboot image.
860 config X86EMU_DEBUG_TRACE
861 bool "Trace all opcodes"
863 depends on X86EMU_DEBUG
865 Print _all_ opcodes that are executed by x86emu.
867 WARNING: This will produce a LOT of output and take a long time.
869 Note: This option will increase the size of the coreboot image.
873 config X86EMU_DEBUG_PNP
874 bool "Log Plug&Play accesses"
876 depends on X86EMU_DEBUG
878 Print Plug And Play accesses made by option ROMs.
880 Note: This option will increase the size of the coreboot image.
884 config X86EMU_DEBUG_DISK
887 depends on X86EMU_DEBUG
889 Print Disk I/O related messages.
891 Note: This option will increase the size of the coreboot image.
895 config X86EMU_DEBUG_PMM
898 depends on X86EMU_DEBUG
900 Print messages related to POST Memory Manager (PMM).
902 Note: This option will increase the size of the coreboot image.
907 config X86EMU_DEBUG_VBE
908 bool "Debug VESA BIOS Extensions"
910 depends on X86EMU_DEBUG
912 Print messages related to VESA BIOS Extension (VBE) functions.
914 Note: This option will increase the size of the coreboot image.
918 config X86EMU_DEBUG_INT10
919 bool "Redirect INT10 output to console"
921 depends on X86EMU_DEBUG
923 Let INT10 (i.e. character output) calls print messages to debug output.
925 Note: This option will increase the size of the coreboot image.
929 config X86EMU_DEBUG_INTERRUPTS
930 bool "Log intXX calls"
932 depends on X86EMU_DEBUG
934 Print messages related to interrupt handling.
936 Note: This option will increase the size of the coreboot image.
940 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
941 bool "Log special memory accesses"
943 depends on X86EMU_DEBUG
945 Print messages related to accesses to certain areas of the virtual
946 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
948 Note: This option will increase the size of the coreboot image.
952 config X86EMU_DEBUG_MEM
953 bool "Log all memory accesses"
955 depends on X86EMU_DEBUG
957 Print memory accesses made by option ROM.
958 Note: This also includes accesses to fetch instructions.
960 Note: This option will increase the size of the coreboot image.
964 config X86EMU_DEBUG_IO
965 bool "Log IO accesses"
967 depends on X86EMU_DEBUG
969 Print I/O accesses made by option ROM.
971 Note: This option will increase the size of the coreboot image.
975 config X86EMU_DEBUG_TIMINGS
976 bool "Output timing information"
978 depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER
980 Print timing information needed by i915tool.
984 config DEBUG_SPI_FLASH
985 bool "Output verbose SPI flash debug messages"
989 This option enables additional SPI flash related debug messages.
991 if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
992 # Only visible with the right southbridge and loglevel.
993 config DEBUG_INTEL_ME
994 bool "Verbose logging for Intel Management Engine"
997 Enable verbose logging for Intel Management Engine driver that
998 is present on Intel 6-series chipsets.
1002 bool "Trace function calls"
1005 If enabled, every function will print information to console once
1006 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
1007 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
1008 of calling function. Please note some printk related functions
1009 are omitted from trace to have good looking console dumps.
1011 config DEBUG_COVERAGE
1012 bool "Debug code coverage"
1016 If enabled, the code coverage hooks in coreboot will output some
1017 information about the coverage data that is dumped.
1019 config DEBUG_BOOT_STATE
1020 bool "Debug boot state machine"
1023 Control debugging of the boot state machine. When selected displays
1024 the state boundaries in ramstage.
1026 config DEBUG_ADA_CODE
1027 bool "Compile debug code in Ada sources"
1030 Add the compiler switch `-gnata` to compile code guarded by
1033 config HAVE_EM100_SUPPORT
1034 bool "Platform can support the Dediprog EM100 SPI emulator"
1036 This is enabled by platforms which can support using the EM100.
1039 bool "Configure image for EM100 usage"
1040 depends on HAVE_EM100_SUPPORT
1042 The Dediprog EM100 SPI emulator allows fast loading of new SPI images
1043 over USB. However it only supports a maximum SPI clock of 20MHz and
1044 single data output. Enable this option to use a 20MHz SPI clock and
1045 disable "Dual Output Fast Read" Support.
1047 On AMD platforms this changes the SPI speed at run-time if the
1048 mainboard code supports this. On supported Intel platforms this works
1049 by changing the settings in the descriptor.bin file.
1054 ###############################################################################
1055 # Set variables with no prompt - these can be set anywhere, and putting at
1056 # the end of this file gives the most flexibility.
1058 source "src/lib/Kconfig"
1060 config ENABLE_APIC_EXT_ID
1064 config WARNINGS_ARE_ERRORS
1068 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1069 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1070 # mutually exclusive. One of these options must be selected in the
1071 # mainboard Kconfig if the chipset supports enabling and disabling of
1072 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1073 # in mainboard/Kconfig to know if the button should be enabled or not.
1075 config POWER_BUTTON_DEFAULT_ENABLE
1078 Select when the board has a power button which can optionally be
1079 disabled by the user.
1081 config POWER_BUTTON_DEFAULT_DISABLE
1084 Select when the board has a power button which can optionally be
1085 enabled by the user, e.g. when the board ships with a jumper over
1086 the power switch contacts.
1088 config POWER_BUTTON_FORCE_ENABLE
1091 Select when the board requires that the power button is always
1094 config POWER_BUTTON_FORCE_DISABLE
1097 Select when the board requires that the power button is always
1098 disabled, e.g. when it has been hardwired to ground.
1100 config POWER_BUTTON_IS_OPTIONAL
1102 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1103 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1105 Internal option that controls ENABLE_POWER_BUTTON visibility.
1111 Internal option that controls whether we compile in register scripts.
1113 config MAX_REBOOT_CNT
1117 Internal option that sets the maximum number of bootblock executions allowed
1118 with the normal image enabled before assuming the normal image is defective
1119 and switching to the fallback image.
1121 config UNCOMPRESSED_RAMSTAGE
1124 config NO_XIP_EARLY_STAGES
1126 default n if ARCH_X86
1129 Identify if early stages are eXecute-In-Place(XIP).
1131 config EARLY_CBMEM_LIST
1135 Enable display of CBMEM during romstage and postcar.
1137 config RELOCATABLE_MODULES
1140 If RELOCATABLE_MODULES is selected then support is enabled for
1141 building relocatable modules in the RAM stage. Those modules can be
1142 loaded anywhere and all the relocations are handled automatically.
1144 config NO_STAGE_CACHE
1146 default y if !HAVE_ACPI_RESUME
1148 Do not save any component in stage cache for resume path. On resume,
1149 all components would be read back from CBFS again.
1151 config GENERIC_GPIO_LIB
1154 If enabled, compile the generic GPIO library. A "generic" GPIO
1155 implies configurability usually found on SoCs, particularly the
1156 ability to control internal pull resistors.
1158 config BOOTBLOCK_CUSTOM
1159 # To be selected by arch, SoC or mainboard if it does not want use the normal
1160 # src/lib/bootblock.c#main() C entry point.
1163 config C_ENVIRONMENT_BOOTBLOCK
1164 # To be selected by arch or platform if a C environment is available during the
1165 # bootblock. Normally this signifies availability of RW memory (e.g. SRAM).
1168 ###############################################################################
1169 # Set default values for symbols created before mainboards. This allows the
1170 # option to be displayed in the general menu, but the default to be loaded in
1171 # the mainboard if desired.
1172 config COMPRESS_RAMSTAGE
1173 default y if !UNCOMPRESSED_RAMSTAGE
1175 config COMPRESS_PRERAM_STAGES
1176 depends on !ARCH_X86
1179 config INCLUDE_CONFIG_FILE
1182 config BOOTSPLASH_FILE
1183 depends on BOOTSPLASH_IMAGE
1184 default "bootsplash.jpg"
1189 config HAVE_BOOTBLOCK
1193 config HAVE_VERSTAGE
1195 depends on VBOOT_SEPARATE_VERSTAGE
1198 config HAVE_ROMSTAGE
1204 depends on POSTCAR_STAGE
1207 config HAVE_RAMSTAGE
1209 default n if RAMPAYLOAD