src/southbridge/intel/bd82x6x/pch.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  * Copyright (C) 2012 The Chromium OS Authors.  All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.
  19  */
  20
  21 #ifndef SOUTHBRIDGE_INTEL_BD82X6X_PCH_H
  22 #define SOUTHBRIDGE_INTEL_BD82X6X_PCH_H
  23
  24 /* PCH types */
  25 #define PCH_TYPE_CPT    0x1c /* CougarPoint */
  26 #define PCH_TYPE_PPT    0x1e /* IvyBridge */
  27
  28 /* PCH stepping values for LPC device */
  29 #define PCH_STEP_A0     0
  30 #define PCH_STEP_A1     1
  31 #define PCH_STEP_B0     2
  32 #define PCH_STEP_B1     3
  33 #define PCH_STEP_B2     4
  34 #define PCH_STEP_B3     5
  35
  36 /*
  37  * It does not matter where we put the SMBus I/O base, as long as we
  38  * keep it consistent and don't interfere with other devices.  Stage2
  39  * will relocate this anyways.
  40  * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
  41  * again. But handling static BARs is a generic problem that should be
  42  * solved in the device allocator.
  43  */
  44 #define SMBUS_IO_BASE           0x0400
  45 #define SMBUS_SLAVE_ADDR        0x24
  46 /* TODO Make sure these don't get changed by stage2 */
  47 #define DEFAULT_GPIOBASE        0x0480
  48 #define DEFAULT_PMBASE          0x0500
  49
  50 #ifndef __ACPI__
  51 #define DEFAULT_RCBA            ((u8 *)0xfed1c000)
  52 #else
  53 #define DEFAULT_RCBA            0xfed1c000
  54 #endif
  55
  56 #ifndef __ACPI__
  57 #define DEBUG_PERIODIC_SMIS 0
  58
  59 #if defined (__SMM__) && !defined(__ASSEMBLER__)
  60 void intel_pch_finalize_smm(void);
  61 #endif
  62
  63 #if !defined(__ASSEMBLER__)
  64 #if !defined(__PRE_RAM__)
  65 #if !defined(__SMM__)
  66 #include "chip.h"
  67 void pch_enable(device_t dev);
  68 #endif
  69 int pch_silicon_revision(void);
  70 int pch_silicon_type(void);
  71 int pch_silicon_supported(int type, int rev);
  72 void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
  73 void gpi_route_interrupt(u8 gpi, u8 mode);
  74 #if CONFIG_ELOG
  75 void pch_log_state(void);
  76 #endif
  77 #else /* __PRE_RAM__ */
  78 void enable_smbus(void);
  79 void enable_usb_bar(void);
  80 int smbus_read_byte(unsigned device, unsigned address);
  81 int early_spi_read(u32 offset, u32 size, u8 *buffer);
  82 void early_thermal_init(void);
  83 void southbridge_configure_default_intmap(void);
  84 void early_pch_init_native(void);
  85 int southbridge_detect_s3_resume(void);
  86
  87 struct southbridge_usb_port
  88 {
  89         int enabled;
  90         int current;
  91         int oc_pin;
  92 };
  93
  94 #ifndef __ROMCC__
  95 extern const struct southbridge_usb_port mainboard_usb_ports[14];
  96 #endif
  97
  98 void
  99 early_usb_init (const struct southbridge_usb_port *portmap);
 100
 101 #endif
 102 #endif
 103
 104 #define MAINBOARD_POWER_OFF     0
 105 #define MAINBOARD_POWER_ON      1
 106 #define MAINBOARD_POWER_KEEP    2
 107
 108 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 109 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
 110 #endif
 111
 112 /* PCI Configuration Space (D30:F0): PCI2PCI */
 113 #define PSTS    0x06
 114 #define SMLT    0x1b
 115 #define SECSTS  0x1e
 116 #define INTR    0x3c
 117 #define BCTRL   0x3e
 118 #define   SBR   (1 << 6)
 119 #define   SEE   (1 << 1)
 120 #define   PERE  (1 << 0)
 121
 122 #define PCH_EHCI1_DEV           PCI_DEV(0, 0x1d, 0)
 123 #define PCH_EHCI2_DEV           PCI_DEV(0, 0x1a, 0)
 124 #define PCH_XHCI_DEV            PCI_DEV(0, 0x14, 0)
 125 #define PCH_ME_DEV              PCI_DEV(0, 0x16, 0)
 126 #define PCH_PCIE_DEV_SLOT       28
 127
 128 /* PCI Configuration Space (D31:F0): LPC */
 129 #define PCH_LPC_DEV             PCI_DEV(0, 0x1f, 0)
 130 #define SERIRQ_CNTL             0x64
 131
 132 #define GEN_PMCON_1             0xa0
 133 #define GEN_PMCON_2             0xa2
 134 #define GEN_PMCON_3             0xa4
 135 #define ETR3                    0xac
 136 #define  ETR3_CWORWRE           (1 << 18)
 137 #define  ETR3_CF9GR             (1 << 20)
 138
 139 /* GEN_PMCON_3 bits */
 140 #define RTC_BATTERY_DEAD        (1 << 2)
 141 #define RTC_POWER_FAILED        (1 << 1)
 142 #define SLEEP_AFTER_POWER_FAIL  (1 << 0)
 143
 144 #define PMBASE                  0x40
 145 #define ACPI_CNTL               0x44
 146 #define   ACPI_EN               (1 << 7)
 147 #define BIOS_CNTL               0xDC
 148 #define GPIO_BASE               0x48 /* LPC GPIO Base Address Register */
 149 #define GPIO_CNTL               0x4C /* LPC GPIO Control Register */
 150
 151 #define GPIO_ROUT               0xb8
 152 #define   GPI_DISABLE           0x00
 153 #define   GPI_IS_SMI            0x01
 154 #define   GPI_IS_SCI            0x02
 155 #define   GPI_IS_NMI            0x03
 156
 157 #define PIRQA_ROUT              0x60
 158 #define PIRQB_ROUT              0x61
 159 #define PIRQC_ROUT              0x62
 160 #define PIRQD_ROUT              0x63
 161 #define PIRQE_ROUT              0x68
 162 #define PIRQF_ROUT              0x69
 163 #define PIRQG_ROUT              0x6A
 164 #define PIRQH_ROUT              0x6B
 165
 166 #define LPC_IO_DEC              0x80 /* IO Decode Ranges Register */
 167 #define LPC_EN                  0x82 /* LPC IF Enables Register */
 168 #define  CNF2_LPC_EN            (1 << 13) /* 0x4e/0x4f */
 169 #define  CNF1_LPC_EN            (1 << 12) /* 0x2e/0x2f */
 170 #define  MC_LPC_EN              (1 << 11) /* 0x62/0x66 */
 171 #define  KBC_LPC_EN             (1 << 10) /* 0x60/0x64 */
 172 #define  GAMEH_LPC_EN           (1 << 9)  /* 0x208/0x20f */
 173 #define  GAMEL_LPC_EN           (1 << 8)  /* 0x200/0x207 */
 174 #define  FDD_LPC_EN             (1 << 3)  /* LPC_IO_DEC[12] */
 175 #define  LPT_LPC_EN             (1 << 2)  /* LPC_IO_DEC[9:8] */
 176 #define  COMB_LPC_EN            (1 << 1)  /* LPC_IO_DEC[6:4] */
 177 #define  COMA_LPC_EN            (1 << 0)  /* LPC_IO_DEC[3:2] */
 178 #define LPC_GEN1_DEC            0x84 /* LPC IF Generic Decode Range 1 */
 179 #define LPC_GEN2_DEC            0x88 /* LPC IF Generic Decode Range 2 */
 180 #define LPC_GEN3_DEC            0x8c /* LPC IF Generic Decode Range 3 */
 181 #define LPC_GEN4_DEC            0x90 /* LPC IF Generic Decode Range 4 */
 182
 183 /* PCI Configuration Space (D31:F1): IDE */
 184 #define PCH_IDE_DEV             PCI_DEV(0, 0x1f, 1)
 185 #define PCH_SATA_DEV            PCI_DEV(0, 0x1f, 2)
 186 #define PCH_SATA2_DEV           PCI_DEV(0, 0x1f, 5)
 187 #define INTR_LN                 0x3c
 188 #define IDE_TIM_PRI             0x40    /* IDE timings, primary */
 189 #define   IDE_DECODE_ENABLE     (1 << 15)
 190 #define   IDE_SITRE             (1 << 14)
 191 #define   IDE_ISP_5_CLOCKS      (0 << 12)
 192 #define   IDE_ISP_4_CLOCKS      (1 << 12)
 193 #define   IDE_ISP_3_CLOCKS      (2 << 12)
 194 #define   IDE_RCT_4_CLOCKS      (0 <<  8)
 195 #define   IDE_RCT_3_CLOCKS      (1 <<  8)
 196 #define   IDE_RCT_2_CLOCKS      (2 <<  8)
 197 #define   IDE_RCT_1_CLOCKS      (3 <<  8)
 198 #define   IDE_DTE1              (1 <<  7)
 199 #define   IDE_PPE1              (1 <<  6)
 200 #define   IDE_IE1               (1 <<  5)
 201 #define   IDE_TIME1             (1 <<  4)
 202 #define   IDE_DTE0              (1 <<  3)
 203 #define   IDE_PPE0              (1 <<  2)
 204 #define   IDE_IE0               (1 <<  1)
 205 #define   IDE_TIME0             (1 <<  0)
 206 #define IDE_TIM_SEC             0x42    /* IDE timings, secondary */
 207
 208 #define IDE_SDMA_CNT            0x48    /* Synchronous DMA control */
 209 #define   IDE_SSDE1             (1 <<  3)
 210 #define   IDE_SSDE0             (1 <<  2)
 211 #define   IDE_PSDE1             (1 <<  1)
 212 #define   IDE_PSDE0             (1 <<  0)
 213
 214 #define IDE_SDMA_TIM            0x4a
 215
 216 #define IDE_CONFIG              0x54    /* IDE I/O Configuration Register */
 217 #define   SIG_MODE_SEC_NORMAL   (0 << 18)
 218 #define   SIG_MODE_SEC_TRISTATE (1 << 18)
 219 #define   SIG_MODE_SEC_DRIVELOW (2 << 18)
 220 #define   SIG_MODE_PRI_NORMAL   (0 << 16)
 221 #define   SIG_MODE_PRI_TRISTATE (1 << 16)
 222 #define   SIG_MODE_PRI_DRIVELOW (2 << 16)
 223 #define   FAST_SCB1             (1 << 15)
 224 #define   FAST_SCB0             (1 << 14)
 225 #define   FAST_PCB1             (1 << 13)
 226 #define   FAST_PCB0             (1 << 12)
 227 #define   SCB1                  (1 <<  3)
 228 #define   SCB0                  (1 <<  2)
 229 #define   PCB1                  (1 <<  1)
 230 #define   PCB0                  (1 <<  0)
 231
 232 #define SATA_SIRI               0xa0 /* SATA Indexed Register Index */
 233 #define SATA_SIRD               0xa4 /* SATA Indexed Register Data */
 234 #define SATA_SP                 0xd0 /* Scratchpad */
 235
 236 /* SATA IOBP Registers */
 237 #define SATA_IOBP_SP0G3IR       0xea000151
 238 #define SATA_IOBP_SP1G3IR       0xea000051
 239
 240 /* PCI Configuration Space (D31:F3): SMBus */
 241 #define PCH_SMBUS_DEV           PCI_DEV(0, 0x1f, 3)
 242 #define SMB_BASE                0x20
 243 #define HOSTC                   0x40
 244 #define SMB_RCV_SLVA            0x09
 245
 246 /* HOSTC bits */
 247 #define I2C_EN                  (1 << 2)
 248 #define SMB_SMI_EN              (1 << 1)
 249 #define HST_EN                  (1 << 0)
 250
 251 /* SMBus I/O bits. */
 252 #define SMBHSTSTAT              0x0
 253 #define SMBHSTCTL               0x2
 254 #define SMBHSTCMD               0x3
 255 #define SMBXMITADD              0x4
 256 #define SMBHSTDAT0              0x5
 257 #define SMBHSTDAT1              0x6
 258 #define SMBBLKDAT               0x7
 259 #define SMBTRNSADD              0x9
 260 #define SMBSLVDATA              0xa
 261 #define SMLINK_PIN_CTL          0xe
 262 #define SMBUS_PIN_CTL           0xf
 263
 264 #define SMBUS_TIMEOUT           (10 * 1000 * 100)
 265
 266
 267 /* Southbridge IO BARs */
 268
 269 #define GPIOBASE                0x48
 270
 271 #define PMBASE          0x40
 272
 273 /* Root Complex Register Block */
 274 #define RCBA            0xf0
 275
 276 #define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
 277 #define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
 278 #define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
 279
 280 #define RCBA_AND_OR(bits, x, and, or) \
 281         RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
 282 #define RCBA8_AND_OR(x, and, or)  RCBA_AND_OR(8, x, and, or)
 283 #define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
 284 #define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
 285 #define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
 286
 287 #define VCH             0x0000  /* 32bit */
 288 #define VCAP1           0x0004  /* 32bit */
 289 #define VCAP2           0x0008  /* 32bit */
 290 #define PVC             0x000c  /* 16bit */
 291 #define PVS             0x000e  /* 16bit */
 292
 293 #define V0CAP           0x0010  /* 32bit */
 294 #define V0CTL           0x0014  /* 32bit */
 295 #define V0STS           0x001a  /* 16bit */
 296
 297 #define V1CAP           0x001c  /* 32bit */
 298 #define V1CTL           0x0020  /* 32bit */
 299 #define V1STS           0x0026  /* 16bit */
 300
 301 #define RCTCL           0x0100  /* 32bit */
 302 #define ESD             0x0104  /* 32bit */
 303 #define ULD             0x0110  /* 32bit */
 304 #define ULBA            0x0118  /* 64bit */
 305
 306 #define RP1D            0x0120  /* 32bit */
 307 #define RP1BA           0x0128  /* 64bit */
 308 #define RP2D            0x0130  /* 32bit */
 309 #define RP2BA           0x0138  /* 64bit */
 310 #define RP3D            0x0140  /* 32bit */
 311 #define RP3BA           0x0148  /* 64bit */
 312 #define RP4D            0x0150  /* 32bit */
 313 #define RP4BA           0x0158  /* 64bit */
 314 #define HDD             0x0160  /* 32bit */
 315 #define HDBA            0x0168  /* 64bit */
 316 #define RP5D            0x0170  /* 32bit */
 317 #define RP5BA           0x0178  /* 64bit */
 318 #define RP6D            0x0180  /* 32bit */
 319 #define RP6BA           0x0188  /* 64bit */
 320
 321 #define RPC             0x0400  /* 32bit */
 322 #define RPFN            0x0404  /* 32bit */
 323
 324 /* Root Port configuratinon space hide */
 325 #define RPFN_HIDE(port)         (1 << (((port) * 4) + 3))
 326 /* Get the function number assigned to a Root Port */
 327 #define RPFN_FNGET(reg,port)    (((reg) >> ((port) * 4)) & 7)
 328 /* Set the function number for a Root Port */
 329 #define RPFN_FNSET(port,func)   (((func) & 7) << ((port) * 4))
 330 /* Root Port function number mask */
 331 #define RPFN_FNMASK(port)       (7 << ((port) * 4))
 332
 333 #define TRSR            0x1e00  /*  8bit */
 334 #define TRCR            0x1e10  /* 64bit */
 335 #define TWDR            0x1e18  /* 64bit */
 336
 337 #define IOTR0           0x1e80  /* 64bit */
 338 #define IOTR1           0x1e88  /* 64bit */
 339 #define IOTR2           0x1e90  /* 64bit */
 340 #define IOTR3           0x1e98  /* 64bit */
 341
 342 #define TCTL            0x3000  /*  8bit */
 343
 344 #define NOINT           0
 345 #define INTA            1
 346 #define INTB            2
 347 #define INTC            3
 348 #define INTD            4
 349
 350 #define DIR_IDR         12      /* Interrupt D Pin Offset */
 351 #define DIR_ICR         8       /* Interrupt C Pin Offset */
 352 #define DIR_IBR         4       /* Interrupt B Pin Offset */
 353 #define DIR_IAR         0       /* Interrupt A Pin Offset */
 354
 355 #define PIRQA           0
 356 #define PIRQB           1
 357 #define PIRQC           2
 358 #define PIRQD           3
 359 #define PIRQE           4
 360 #define PIRQF           5
 361 #define PIRQG           6
 362 #define PIRQH           7
 363
 364 /* IO Buffer Programming */
 365 #define IOBPIRI         0x2330
 366 #define IOBPD           0x2334
 367 #define IOBPS           0x2338
 368 #define  IOBPS_RW_BX    ((1 << 9)|(1 << 10))
 369 #define  IOBPS_WRITE_AX ((1 << 9)|(1 << 10))
 370 #define  IOBPS_READ_AX  ((1 << 8)|(1 << 9)|(1 << 10))
 371
 372 #define D31IP           0x3100  /* 32bit */
 373 #define D31IP_TTIP      24      /* Thermal Throttle Pin */
 374 #define D31IP_SIP2      20      /* SATA Pin 2 */
 375 #define D31IP_SMIP      12      /* SMBUS Pin */
 376 #define D31IP_SIP       8       /* SATA Pin */
 377 #define D30IP           0x3104  /* 32bit */
 378 #define D30IP_PIP       0       /* PCI Bridge Pin */
 379 #define D29IP           0x3108  /* 32bit */
 380 #define D29IP_E1P       0       /* EHCI #1 Pin */
 381 #define D28IP           0x310c  /* 32bit */
 382 #define D28IP_P8IP      28      /* PCI Express Port 8 */
 383 #define D28IP_P7IP      24      /* PCI Express Port 7 */
 384 #define D28IP_P6IP      20      /* PCI Express Port 6 */
 385 #define D28IP_P5IP      16      /* PCI Express Port 5 */
 386 #define D28IP_P4IP      12      /* PCI Express Port 4 */
 387 #define D28IP_P3IP      8       /* PCI Express Port 3 */
 388 #define D28IP_P2IP      4       /* PCI Express Port 2 */
 389 #define D28IP_P1IP      0       /* PCI Express Port 1 */
 390 #define D27IP           0x3110  /* 32bit */
 391 #define D27IP_ZIP       0       /* HD Audio Pin */
 392 #define D26IP           0x3114  /* 32bit */
 393 #define D26IP_E2P       0       /* EHCI #2 Pin */
 394 #define D25IP           0x3118  /* 32bit */
 395 #define D25IP_LIP       0       /* GbE LAN Pin */
 396 #define D22IP           0x3124  /* 32bit */
 397 #define D22IP_KTIP      12      /* KT Pin */
 398 #define D22IP_IDERIP    8       /* IDE-R Pin */
 399 #define D22IP_MEI2IP    4       /* MEI #2 Pin */
 400 #define D22IP_MEI1IP    0       /* MEI #1 Pin */
 401 #define D20IP           0x3128  /* 32bit */
 402 #define D20IP_XHCIIP    0
 403 #define D31IR           0x3140  /* 16bit */
 404 #define D30IR           0x3142  /* 16bit */
 405 #define D29IR           0x3144  /* 16bit */
 406 #define D28IR           0x3146  /* 16bit */
 407 #define D27IR           0x3148  /* 16bit */
 408 #define D26IR           0x314c  /* 16bit */
 409 #define D25IR           0x3150  /* 16bit */
 410 #define D22IR           0x315c  /* 16bit */
 411 #define D20IR           0x3160  /* 16bit */
 412 #define OIC             0x31fe  /* 16bit */
 413 #define SOFT_RESET_CTRL 0x38f4
 414 #define SOFT_RESET_DATA 0x38f8
 415
 416 #define DIR_ROUTE(x,a,b,c,d) \
 417   RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
 418                ((b) << DIR_IBR) | ((a) << DIR_IAR))
 419
 420 #define RC              0x3400  /* 32bit */
 421 #define HPTC            0x3404  /* 32bit */
 422 #define GCS             0x3410  /* 32bit */
 423 #define BUC             0x3414  /* 32bit */
 424 #define PCH_DISABLE_GBE         (1 << 5)
 425 #define FD              0x3418  /* 32bit */
 426 #define DISPBDF         0x3424  /* 16bit */
 427 #define FD2             0x3428  /* 32bit */
 428 #define CG              0x341c  /* 32bit */
 429
 430 /* Function Disable 1 RCBA 0x3418 */
 431 #define PCH_DISABLE_ALWAYS      ((1 << 0)|(1 << 26))
 432 #define PCH_DISABLE_P2P         (1 << 1)
 433 #define PCH_DISABLE_SATA1       (1 << 2)
 434 #define PCH_DISABLE_SMBUS       (1 << 3)
 435 #define PCH_DISABLE_HD_AUDIO    (1 << 4)
 436 #define PCH_DISABLE_EHCI2       (1 << 13)
 437 #define PCH_DISABLE_LPC         (1 << 14)
 438 #define PCH_DISABLE_EHCI1       (1 << 15)
 439 #define PCH_DISABLE_PCIE(x)     (1 << (16 + x))
 440 #define PCH_DISABLE_THERMAL     (1 << 24)
 441 #define PCH_DISABLE_SATA2       (1 << 25)
 442 #define PCH_DISABLE_XHCI        (1 << 27)
 443
 444 /* Function Disable 2 RCBA 0x3428 */
 445 #define PCH_DISABLE_KT          (1 << 4)
 446 #define PCH_DISABLE_IDER        (1 << 3)
 447 #define PCH_DISABLE_MEI2        (1 << 2)
 448 #define PCH_DISABLE_MEI1        (1 << 1)
 449 #define PCH_ENABLE_DBDF         (1 << 0)
 450
 451 /* USB Port Disable Override */
 452 #define USBPDO          0x359c  /* 32bit */
 453 /* USB Overcurrent MAP Register */
 454 #define USBOCM1         0x35a0  /* 32bit */
 455 #define USBOCM2         0x35a4  /* 32bit */
 456
 457 /* XHCI USB 3.0 */
 458 #define XOCM            0xc0    /* 32bit */
 459 #define XUSB2PRM        0xd4    /* 32bit */
 460 #define USB3PRM         0xdc    /* 32bit */
 461
 462 /* ICH7 GPIOBASE */
 463 #define GPIO_USE_SEL    0x00
 464 #define GP_IO_SEL       0x04
 465 #define GP_LVL          0x0c
 466 #define GPO_BLINK       0x18
 467 #define GPI_INV         0x2c
 468 #define GPIO_USE_SEL2   0x30
 469 #define GP_IO_SEL2      0x34
 470 #define GP_LVL2         0x38
 471 #define GPIO_USE_SEL3   0x40
 472 #define GP_IO_SEL3      0x44
 473 #define GP_LVL3         0x48
 474 #define GP_RST_SEL1     0x60
 475 #define GP_RST_SEL2     0x64
 476 #define GP_RST_SEL3     0x68
 477
 478 /* ICH7 PMBASE */
 479 #define PM1_STS         0x00
 480 #define   WAK_STS       (1 << 15)
 481 #define   PCIEXPWAK_STS (1 << 14)
 482 #define   PRBTNOR_STS   (1 << 11)
 483 #define   RTC_STS       (1 << 10)
 484 #define   PWRBTN_STS    (1 << 8)
 485 #define   GBL_STS       (1 << 5)
 486 #define   BM_STS        (1 << 4)
 487 #define   TMROF_STS     (1 << 0)
 488 #define PM1_EN          0x02
 489 #define   PCIEXPWAK_DIS (1 << 14)
 490 #define   RTC_EN        (1 << 10)
 491 #define   PWRBTN_EN     (1 << 8)
 492 #define   GBL_EN        (1 << 5)
 493 #define   TMROF_EN      (1 << 0)
 494 #define PM1_CNT         0x04
 495 #define   SLP_EN        (1 << 13)
 496 #define   SLP_TYP       (7 << 10)
 497 #define    SLP_TYP_S0   0
 498 #define    SLP_TYP_S1   1
 499 #define    SLP_TYP_S3   5
 500 #define    SLP_TYP_S4   6
 501 #define    SLP_TYP_S5   7
 502 #define   GBL_RLS       (1 << 2)
 503 #define   BM_RLD        (1 << 1)
 504 #define   SCI_EN        (1 << 0)
 505 #define PM1_TMR         0x08
 506 #define PROC_CNT        0x10
 507 #define LV2             0x14
 508 #define LV3             0x15
 509 #define LV4             0x16
 510 #define PM2_CNT         0x50 // mobile only
 511 #define GPE0_STS        0x20
 512 #define   PME_B0_STS    (1 << 13)
 513 #define   PME_STS       (1 << 11)
 514 #define   BATLOW_STS    (1 << 10)
 515 #define   PCI_EXP_STS   (1 << 9)
 516 #define   RI_STS        (1 << 8)
 517 #define   SMB_WAK_STS   (1 << 7)
 518 #define   TCOSCI_STS    (1 << 6)
 519 #define   SWGPE_STS     (1 << 2)
 520 #define   HOT_PLUG_STS  (1 << 1)
 521 #define GPE0_EN         0x28
 522 #define   PME_B0_EN     (1 << 13)
 523 #define   PME_EN        (1 << 11)
 524 #define   TCOSCI_EN     (1 << 6)
 525 #define SMI_EN          0x30
 526 #define   INTEL_USB2_EN  (1 << 18) // Intel-Specific USB2 SMI logic
 527 #define   LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
 528 #define   PERIODIC_EN    (1 << 14) // SMI on PERIODIC_STS in SMI_STS
 529 #define   TCO_EN         (1 << 13) // Enable TCO Logic (BIOSWE et al)
 530 #define   MCSMI_EN       (1 << 11) // Trap microcontroller range access
 531 #define   BIOS_RLS       (1 <<  7) // asserts SCI on bit set
 532 #define   SWSMI_TMR_EN   (1 <<  6) // start software smi timer on bit set
 533 #define   APMC_EN        (1 <<  5) // Writes to APM_CNT cause SMI#
 534 #define   SLP_SMI_EN     (1 <<  4) // Write to SLP_EN in PM1_CNT asserts SMI#
 535 #define   LEGACY_USB_EN  (1 <<  3) // Legacy USB circuit SMI logic
 536 #define   BIOS_EN        (1 <<  2) // Assert SMI# on setting GBL_RLS bit
 537 #define   EOS            (1 <<  1) // End of SMI (deassert SMI#)
 538 #define   GBL_SMI_EN     (1 <<  0) // SMI# generation at all?
 539 #define SMI_STS         0x34
 540 #define ALT_GP_SMI_EN   0x38
 541 #define ALT_GP_SMI_STS  0x3a
 542 #define GPE_CNTL        0x42
 543 #define DEVACT_STS      0x44
 544 #define SS_CNT          0x50
 545 #define C3_RES          0x54
 546 #define TCO1_STS        0x64
 547 #define   DMISCI_STS    (1 << 9)
 548 #define TCO2_STS        0x66
 549
 550 /*
 551  * SPI Opcode Menu setup for SPIBAR lockdown
 552  * should support most common flash chips.
 553  */
 554
 555 #define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
 556 #define SPI_OPTYPE_0 0x01 /* Write, no address */
 557
 558 #define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
 559 #define SPI_OPTYPE_1 0x03 /* Write, address required */
 560
 561 #define SPI_OPMENU_2 0x03 /* READ: Read Data */
 562 #define SPI_OPTYPE_2 0x02 /* Read, address required */
 563
 564 #define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
 565 #define SPI_OPTYPE_3 0x00 /* Read, no address */
 566
 567 #define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
 568 #define SPI_OPTYPE_4 0x03 /* Write, address required */
 569
 570 #define SPI_OPMENU_5 0x9f /* RDID: Read ID */
 571 #define SPI_OPTYPE_5 0x00 /* Read, no address */
 572
 573 #define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
 574 #define SPI_OPTYPE_6 0x03 /* Write, address required */
 575
 576 #define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
 577 #define SPI_OPTYPE_7 0x02 /* Read, address required */
 578
 579 #define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
 580                           (SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
 581 #define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
 582                           (SPI_OPMENU_1 << 8) | SPI_OPMENU_0)
 583
 584 #define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
 585                     (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) |  \
 586                     (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) |   \
 587                     (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
 588
 589 #define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
 590
 591 #define SPIBAR_HSFS                 0x3804   /* SPI hardware sequence status */
 592 #define  SPIBAR_HSFS_SCIP           (1 << 5) /* SPI Cycle In Progress */
 593 #define  SPIBAR_HSFS_AEL            (1 << 2) /* SPI Access Error Log */
 594 #define  SPIBAR_HSFS_FCERR          (1 << 1) /* SPI Flash Cycle Error */
 595 #define  SPIBAR_HSFS_FDONE          (1 << 0) /* SPI Flash Cycle Done */
 596 #define SPIBAR_HSFC                 0x3806   /* SPI hardware sequence control */
 597 #define  SPIBAR_HSFC_BYTE_COUNT(c)  (((c - 1) & 0x3f) << 8)
 598 #define  SPIBAR_HSFC_CYCLE_READ     (0 << 1) /* Read cycle */
 599 #define  SPIBAR_HSFC_CYCLE_WRITE    (2 << 1) /* Write cycle */
 600 #define  SPIBAR_HSFC_CYCLE_ERASE    (3 << 1) /* Erase cycle */
 601 #define  SPIBAR_HSFC_GO             (1 << 0) /* GO: start SPI transaction */
 602 #define SPIBAR_FADDR                0x3808   /* SPI flash address */
 603 #define SPIBAR_FDATA(n)             (0x3810 + (4 * n)) /* SPI flash data */
 604
 605 #endif /* __ACPI__ */
 606 #endif                          /* SOUTHBRIDGE_INTEL_BD82X6X_PCH_H */