src/southbridge/amd/sr5650/sr5650.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc.
  18  */
  19
  20 #ifndef __SR5650_H__
  21 #define __SR5650_H__
  22
  23 #include <stdint.h>
  24 #include <device/pci_ids.h>
  25 #include "chip.h"
  26 #include "rev.h"
  27
  28 typedef struct __PCIE_CFG__ {
  29         u16 Config;
  30         u8 ResetReleaseDelay;
  31         u8 Gfx0Width;
  32         u8 Gfx1Width;
  33         u8 GfxPayload;
  34         u8 GppPayload;
  35         u16 PortDetect;
  36         u8 PortHp;              /* hot plug */
  37         u16 DbgConfig;
  38         u32 DbgConfig2;
  39         u8 GfxLx;
  40         u8 GppLx;
  41         u8 NBSBLx;
  42         u8 PortSlotInit;
  43         u8 Gfx0Pwr;
  44         u8 Gfx1Pwr;
  45         u8 GppPwr;
  46 } PCIE_CFG;
  47
  48 /* PCIE config flags */
  49 #define PCIE_DUALSLOT_CONFIG            (1 << 0)
  50 #define PCIE_OVERCLOCK_ENABLE           (1 << 1)
  51 #define PCIE_GPP_CLK_GATING             (1 << 2)
  52 #define PCIE_ENABLE_STATIC_DEV_REMAP    (1 << 3)
  53 #define PCIE_OFF_UNUSED_GFX_LANES       (1 << 4)
  54 #define PCIE_OFF_UNUSED_GPP_LANES       (1 << 5)
  55 #define PCIE_DISABLE_HIDE_UNUSED_PORTS  (1 << 7)
  56 #define PCIE_GFX_CLK_GATING             (1 << 11)
  57 #define PCIE_GFX_COMPLIANCE             (1 << 14)
  58 #define PCIE_GPP_COMPLIANCE             (1 << 15)
  59
  60 /* -------------------- ----------------------
  61 * NBMISCIND
  62  ------------------- -----------------------*/
  63 #define PCIE_LINK_CFG                   0x8
  64 #define PCIE_NBCFG_REG7                 0x37
  65 #define STRAPS_OUTPUT_MUX_7             0x67
  66 #define STRAPS_OUTPUT_MUX_A             0x6a
  67
  68 /* -------------------- ----------------------
  69 * PCIEIND
  70  ------------------- -----------------------*/
  71 #define PCIE_CI_CNTL                    0x20
  72 #define PCIE_LC_LINK_WIDTH              0xa2
  73 #define PCIE_LC_STATE0                  0xa5
  74 #define PCIE_VC0_RESOURCE_STATUS        0x12a   /* 16bit read only */
  75
  76 #define PCIE_CORE_INDEX_SB              (0x05 << 16) /* see rpr 4.3.2.2, bdg 2.1 */
  77 #define PCIE_CORE_INDEX_GPP1            (0x04 << 16)
  78 #define PCIE_CORE_INDEX_GPP2            (0x06 << 16)
  79 #define PCIE_CORE_INDEX_GPP1_GPP2       (0x00 << 16)
  80 #define PCIE_CORE_INDEX_GPP3a           (0x07 << 16)
  81 #define PCIE_CORE_INDEX_GPP3b           (0x03 << 16)
  82
  83 /* contents of PCIE_VC0_RESOURCE_STATUS */
  84 #define VC_NEGOTIATION_PENDING          (1 << 1)
  85
  86 #define LC_STATE_RECONFIG_GPPSB         0x10
  87
  88 /* ------------------------------------------------
  89 * Global variable
  90 * ------------------------------------------------- */
  91 extern PCIE_CFG AtiPcieCfg;
  92
  93 /* ----------------- export functions ----------------- */
  94 u32 nbpcie_p_read_index(device_t dev, u32 index);
  95 void nbpcie_p_write_index(device_t dev, u32 index, u32 data);
  96 u32 nbpcie_ind_read_index(device_t nb_dev, u32 index);
  97 void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data);
  98 u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg);
  99 void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg, u32 mask, u32 val);
 100 void sr5650_set_tom(device_t nb_dev);
 101
 102 void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add);
 103 void enable_pcie_bar3(device_t nb_dev);
 104 void disable_pcie_bar3(device_t nb_dev);
 105
 106 void enable_sr5650_dev8(void);
 107 void sr5650_htinit(void);
 108 void sr5650_early_setup(void);
 109 void sr5650_before_pci_init(void);
 110 void sr5650_enable(device_t dev);
 111 void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port);
 112 void sr5650_gfx_init(device_t nb_dev, device_t dev, u32 port);
 113 void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev);
 114 void config_gpp_core(device_t nb_dev, device_t sb_dev);
 115 void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port);
 116 u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port);
 117 void pcie_config_misc_clk(device_t nb_dev);
 118 void fam10_optimization(void);
 119 void sr5650_disable_pcie_bridge(void);
 120 u32 get_vid_did(device_t dev);
 121 void sr5650_nb_pci_table(device_t nb_dev);
 122 void init_gen2(device_t nb_dev, device_t dev, u8 port);
 123 void sr56x0_lock_hwinitreg(void);
 124 #endif /* SR5650_H */