src/southbridge/amd/sb800/pci.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc.
  18  */
  19
  20 #include <console/console.h>
  21 #include <device/device.h>
  22 #include <device/pci.h>
  23 #include <device/pci_ids.h>
  24 #include <device/pci_ops.h>
  25 #include "sb800.h"
  26
  27 static void pci_init(struct device *dev)
  28 {
  29         u32 dword;
  30         u8 byte;
  31
  32         /* RPR 6.1 Enables the PCI-bridge subtractive decode */
  33         /* This setting is strongly recommended since it supports some legacy PCI add-on cards,such as BIOS debug cards */
  34         byte = pci_read_config8(dev, 0x4B);
  35         byte |= 1 << 7;
  36         pci_write_config8(dev, 0x4B, byte);
  37         byte = pci_read_config8(dev, 0x40);
  38         byte |= 1 << 5;
  39         pci_write_config8(dev, 0x40, byte);
  40
  41         /* RPR6.2 PCI-bridge upstream dual address window */
  42         /* this setting is applicable if the system memory is more than 4GB,and the PCI device can support dual address access */
  43         byte = pci_read_config8(dev, 0x50);
  44         byte |= 1 << 0;
  45         pci_write_config8(dev, 0x50, byte);
  46
  47         /* RPR 6.3 Enable One-Prefetch-Channel Mode */
  48         dword = pci_read_config32(dev, 0x64);
  49         dword |= 1 << 20;
  50         pci_write_config32(dev, 0x64, dword);
  51
  52         /* rpr6.4 Adjusting CLKRUN# */
  53         dword = pci_read_config32(dev, 0x64);
  54         dword |= (1 << 15);
  55         pci_write_config32(dev, 0x64, dword);
  56 }
  57
  58 static struct pci_operations lops_pci = {
  59         .set_subsystem = 0,
  60 };
  61
  62 static struct device_operations pci_ops = {
  63         .read_resources = pci_bus_read_resources,
  64         .set_resources = pci_dev_set_resources,
  65         .enable_resources = pci_bus_enable_resources,
  66         .init = pci_init,
  67         .scan_bus = pci_scan_bridge,
  68         .reset_bus = pci_bus_reset,
  69         .ops_pci = &lops_pci,
  70 };
  71
  72 static const struct pci_driver pci_driver __pci_driver = {
  73         .ops = &pci_ops,
  74         .vendor = PCI_VENDOR_ID_ATI,
  75         .device = PCI_DEVICE_ID_ATI_SB800_PCI,
  76 };