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Remove address from GPLv2 headers
[coreboot.git] / src / southbridge / amd / rs780 / rs780.c
blobc7003c79164c89ddfb915d4d067e1ede9d5b9706
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc.
18 */
19
20 #include <console/console.h>
21 #include <arch/io.h>
22 #include <device/device.h>
23 #include <device/pci.h>
24 #include <device/pci_ids.h>
25 #include <device/pci_ops.h>
26 #include <cpu/x86/msr.h>
27 #include <cpu/amd/mtrr.h>
28 #include "rs780.h"
29
30 /*****************************************
31 * rs780_config_misc_clk()
32 *****************************************/
33 void static rs780_config_misc_clk(device_t nb_dev)
34 {
35 u32 reg;
36 u16 word;
37 u8 byte;
38 struct bus pbus; /* fake bus for dev0 fun1 */
39
40 reg = pci_read_config32(nb_dev, 0x4c);
41 reg |= 1 << 0;
42 pci_write_config32(nb_dev, 0x4c, reg);
43
44 word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xf8);
45 word &= 0xf00;
46 pci_cf8_conf1.write16(&pbus, 0, 1, 0xf8, word);
47
48 word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xe8);
49 word &= ~((1 << 12) | (1 << 13) | (1 << 14));
50 word |= 1 << 13;
51 pci_cf8_conf1.write16(&pbus, 0, 1, 0xe8, word);
52
53 reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
54 reg &= ~((1 << 16) | (1 << 24) | (1 << 28));
55 pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
56
57 reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c);
58 reg &= ~((1 << 13) | (1 << 14) | (1 << 24) | (1 << 25));
59 reg |= 1 << 13;
60 pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg);
61
62 reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
63 reg |= 1 << 24;
64 pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
65
66 reg = nbmc_read_index(nb_dev, 0x7a);
67 reg &= ~0x3f;
68 reg |= 1 << 2;
69 reg &= ~(1 << 6);
70 set_htiu_enable_bits(nb_dev, 0x05, 1 << 11, 1 << 11);
71 nbmc_write_index(nb_dev, 0x7a, reg);
72 /* Powering Down efuse and strap block clocks after boot-up. GFX Mode. */
73 reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
74 reg &= ~(1 << 23);
75 reg |= 1 << 24;
76 pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
77
78 /* Programming NB CLK table. */
79 byte = pci_cf8_conf1.read8(&pbus, 0, 1, 0xe0);
80 byte |= 0x01;
81 pci_cf8_conf1.write8(&pbus, 0, 1, 0xe0, byte);
82
83 #if 0
84 /* Powerdown reference clock to graphics core PLL in northbridge only mode */
85 reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c);
86 reg |= 1 << 21;
87 pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg);
88
89 /* Powering Down efuse and strap block clocks after boot-up. NB Only Mode. */
90 reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
91 reg |= (1 << 23) | (1 << 24);
92 pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
93
94 /* Powerdown clock to memory controller in northbridge only mode */
95 byte = pci_cf8_conf1.read8(&pbus, 0, 1, 0xe4);
96 byte |= 1 << 0;
97 pci_cf8_conf1.write8(&pbus, 0, 1, 0xe4, reg);
98
99 /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */
100 /* TODO: */
101 #endif
102
103 reg = pci_read_config32(nb_dev, 0x4c);
104 reg &= ~(1 << 0);
105 pci_write_config32(nb_dev, 0x4c, reg);
106
107 set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8);
108 }
109
110 static u32 get_vid_did(device_t dev)
111 {
112 return pci_read_config32(dev, 0);
113 }
114
115 static void rs780_nb_pci_table(device_t nb_dev)
116 { /* NBPOR_InitPOR function. */
117 u8 temp8;
118 u16 temp16;
119 u32 temp32;
120
121 /* Program NB PCI table. */
122 temp16 = pci_read_config16(nb_dev, 0x04);
123 printk(BIOS_DEBUG, "NB_PCI_REG04 = %x.\n", temp16);
124 temp32 = pci_read_config32(nb_dev, 0x84);
125 printk(BIOS_DEBUG, "NB_PCI_REG84 = %x.\n", temp32);
126
127 pci_write_config8(nb_dev, 0x4c, 0x42);
128
129 temp8 = pci_read_config8(nb_dev, 0x4e);
130 temp8 |= 0x05;
131 pci_write_config8(nb_dev, 0x4e, temp8);
132
133 temp32 = pci_read_config32(nb_dev, 0x4c);
134 printk(BIOS_DEBUG, "NB_PCI_REG4C = %x.\n", temp32);
135
136 /* set temporary NB TOM to 0x40000000. */
137 rs780_set_tom(nb_dev);
138
139 /* Program NB HTIU table. */
140 #if 0
141 set_htiu_enable_bits(nb_dev, 0x05, 1<<10 | 1<<9, 1<<10|1<<9);
142 set_htiu_enable_bits(nb_dev, 0x06, 1, 0x4203a202);
143 set_htiu_enable_bits(nb_dev, 0x07, 1<<1 | 1<<2, 0x8001);
144 set_htiu_enable_bits(nb_dev, 0x15, 0, 1<<31 | 1<<30 | 1<<27);
145 set_htiu_enable_bits(nb_dev, 0x1c, 0, 0xfffe0000);
146 set_htiu_enable_bits(nb_dev, 0x4b, 1<<11, 1<<11);
147 set_htiu_enable_bits(nb_dev, 0x0c, 0x3f, 1 | 1<<3);
148 set_htiu_enable_bits(nb_dev, 0x17, 1<<1 | 1<<27, 1<<1);
149 set_htiu_enable_bits(nb_dev, 0x17, 0, 1<<30);
150 set_htiu_enable_bits(nb_dev, 0x19, 0xfffff+(1<<31), 0x186a0+(1<<31));
151 set_htiu_enable_bits(nb_dev, 0x16, 0x3f<<10, 0x7<<10);
152 set_htiu_enable_bits(nb_dev, 0x23, 0, 1<<28);
153
154 /* Program NB MISC table. */
155 set_nbmisc_enable_bits(nb_dev, 0x0b, 0xffff, 0x00000180);
156 set_nbmisc_enable_bits(nb_dev, 0x00, 0xffff, 0x00000106);
157 set_nbmisc_enable_bits(nb_dev, 0x51, 0xffffffff, 0x00100100);
158 set_nbmisc_enable_bits(nb_dev, 0x53, 0xffffffff, 0x00100100);
159 set_nbmisc_enable_bits(nb_dev, 0x55, 0xffffffff, 0x00100100);
160 set_nbmisc_enable_bits(nb_dev, 0x57, 0xffffffff, 0x00100100);
161 set_nbmisc_enable_bits(nb_dev, 0x59, 0xffffffff, 0x00100100);
162 set_nbmisc_enable_bits(nb_dev, 0x5b, 0xffffffff, 0x00100100);
163 set_nbmisc_enable_bits(nb_dev, 0x5d, 0xffffffff, 0x00100100);
164 set_nbmisc_enable_bits(nb_dev, 0x5f, 0xffffffff, 0x00100100);
165 set_nbmisc_enable_bits(nb_dev, 0x20, 1<<1, 0);
166 set_nbmisc_enable_bits(nb_dev, 0x37, 1<<11|1<<12|1<<13|1<<26, 0);
167 set_nbmisc_enable_bits(nb_dev, 0x68, 1<<5|1<<6, 1<<5);
168 set_nbmisc_enable_bits(nb_dev, 0x6b, 1<<22, 1<<10);
169 set_nbmisc_enable_bits(nb_dev, 0x67, 1<<26, 1<<14|1<<10);
170 set_nbmisc_enable_bits(nb_dev, 0x24, 1<<28|1<<26|1<<25|1<<16, 1<<29|1<<25);
171 set_nbmisc_enable_bits(nb_dev, 0x38, 1<<24|1<<25, 1<<24);
172 set_nbmisc_enable_bits(nb_dev, 0x36, 1<<29, 1<<29|1<<28);
173 set_nbmisc_enable_bits(nb_dev, 0x0c, 0, 1<<13);
174 set_nbmisc_enable_bits(nb_dev, 0x34, 1<<22, 1<<10);
175 set_nbmisc_enable_bits(nb_dev, 0x39, 1<<10, 1<<30);
176 set_nbmisc_enable_bits(nb_dev, 0x22, 1<<3, 0);
177 set_nbmisc_enable_bits(nb_dev, 0x68, 1<<19, 0);
178 set_nbmisc_enable_bits(nb_dev, 0x24, 1<<16|1<<17, 1<<17);
179 set_nbmisc_enable_bits(nb_dev, 0x6a, 1<<22|1<<23, 1<<17|1<<23);
180 set_nbmisc_enable_bits(nb_dev, 0x35, 1<<21|1<<22, 1<<22);
181 set_nbmisc_enable_bits(nb_dev, 0x01, 0xffffffff, 0x48);
182
183 /* the last two step. */
184 set_nbmisc_enable_bits(nb_dev, 0x01, 1<<8, 1<<8);
185 set_htiu_enable_bits(nb_dev, 0x2d, 1<<6|1<<4, 1<<6|1<<4);
186 #endif
187 }
188
189 static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
190 {
191 /* NB_InitGFXStraps */
192 u32 MMIOBase, apc04, apc18, apc24, romstrap2;
193 volatile u32 * strap;
194
195 /* Choose a base address that is unused and routed to the RS780. */
196 MMIOBase = 0xFFB00000;
197
198 /* 1E: NB_BIF_SPARE */
199 set_nbmisc_enable_bits(nb_dev, 0x1e, 0xffffffff, 1<<1 | 1<<4 | 1<<6 | 1<<7);
200 /* Set a temporary Bus number. */
201 apc18 = pci_read_config32(dev, 0x18);
202 pci_write_config32(dev, 0x18, 0x010100);
203 /* Set MMIO window for AGP target(graphics controller). */
204 apc24 = pci_read_config32(dev, 0x24);
205 pci_write_config32(dev, 0x24, (MMIOBase>>16)+((MMIOBase+0x20000)&0xffff0000));
206 /* Enable memory access. */
207 apc04 = pci_read_config32(dev, 0x04);
208 pci_write_config8(dev, 0x04, 0x02);
209
210 /* Program Straps. */
211 romstrap2 = 1 << 26; // enables audio function
212 #if CONFIG_GFXUMA
213 // bits 7-9: aperture size
214 // 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g
215 if (uma_memory_size == 0x02000000) romstrap2 |= 3 << 7;
216 if (uma_memory_size == 0x04000000) romstrap2 |= 2 << 7;
217 if (uma_memory_size == 0x08000000) romstrap2 |= 0 << 7;
218 if (uma_memory_size == 0x10000000) romstrap2 |= 1 << 7;
219 if (uma_memory_size == 0x20000000) romstrap2 |= 4 << 7;
220 if (uma_memory_size == 0x40000000) romstrap2 |= 5 << 7;
221 if (uma_memory_size == 0x80000000) romstrap2 |= 6 << 7;
222 #endif
223 strap = (volatile u32 *)(MMIOBase + 0x15020);
224 *strap = romstrap2;
225 strap = (volatile u32 *)(MMIOBase + 0x15000);
226 *strap = 0x2c006300;
227 strap = (volatile u32 *)(MMIOBase + 0x15010);
228 *strap = 0x03015330;
229 strap = (volatile u32 *)(MMIOBase + 0x15020);
230 *strap = romstrap2 | 0x00000040;
231 strap = (volatile u32 *)(MMIOBase + 0x15030);
232 *strap = 0x00001002;
233 strap = (volatile u32 *)(MMIOBase + 0x15040);
234 *strap = 0x00000000;
235 strap = (volatile u32 *)(MMIOBase + 0x15050);
236 *strap = 0x00000000;
237 strap = (volatile u32 *)(MMIOBase + 0x15220);
238 *strap = 0x03c03800;
239 strap = (volatile u32 *)(MMIOBase + 0x15060);
240 *strap = 0x00000000;
241
242 /* BIF switches into normal functional mode. */
243 set_nbmisc_enable_bits(nb_dev, 0x1e, 1<<4 | 1<<5, 1<<5);
244
245 /* NB Revision is A12 or newer */
246 if (get_nb_rev(nb_dev) >= REV_RS780_A12)
247 set_nbmisc_enable_bits(nb_dev, 0x1e, 1<<9, 1<<9);
248
249 /* Restore APC04, APC18, APC24. */
250 pci_write_config32(dev, 0x04, apc04);
251 pci_write_config32(dev, 0x18, apc18);
252 pci_write_config32(dev, 0x24, apc24);
253
254 printk(BIOS_INFO, "GC is accessible from now on.\n");
255 }
256
257 /***********************************************
258 * 0:00.0 NBCFG :
259 * 0:00.1 CLK : bit 0 of nb_cfg 0x4c : 0 - disable, default
260 * 0:01.0 P2P Internal:
261 * 0:02.0 P2P : bit 2 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
262 * 0:03.0 P2P : bit 3 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
263 * 0:04.0 P2P : bit 4 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
264 * 0:05.0 P2P : bit 5 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
265 * 0:06.0 P2P : bit 6 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
266 * 0:07.0 P2P : bit 7 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
267 * 0:08.0 NB2SB : bit 6 of nbmiscind 0x00 : 0 - disable, default + 32 * 1
268 * case 0 will be called twice, one is by cpu in hypertransport.c line458,
269 * the other is by rs780.
270 ***********************************************/
271 void rs780_enable(device_t dev)
272 {
273 device_t nb_dev = 0, sb_dev = 0;
274 int dev_ind;
275
276 printk(BIOS_INFO, "rs780_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev));
277
278 nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
279 if (!nb_dev) {
280 die("rs780_enable: CAN NOT FIND RS780 DEVICE, HALT!\n");
281 /* NOT REACHED */
282 }
283
284 /* sb_dev (dev 8) is a bridge that links to southbridge. */
285 sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0));
286 if (!sb_dev) {
287 die("rs780_enable: CAN NOT FIND SB bridge, HALT!\n");
288 /* NOT REACHED */
289 }
290
291 dev_ind = dev->path.pci.devfn >> 3;
292 switch (dev_ind) {
293 case 0: /* bus0, dev0, fun0; */
294 printk(BIOS_INFO, "Bus-0, Dev-0, Fun-0.\n");
295 enable_pcie_bar3(nb_dev); /* PCIEMiscInit */
296 config_gpp_core(nb_dev, sb_dev);
297 rs780_gpp_sb_init(nb_dev, sb_dev, 8);
298 /* 5.10.8.4. set SB payload size: 64byte */
299 set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPPSB, 3 << 11, 2 << 11);
300
301 /* Bus0Dev0Fun1Clock control init, we have to do it here, for dev0 Fun1 doesn't have a vendor or device ID */
302 rs780_config_misc_clk(nb_dev);
303
304 rs780_nb_pci_table(nb_dev);
305 break;
306
307 case 1: /* bus0, dev1, APC. */
308 printk(BIOS_INFO, "Bus-0, Dev-1, Fun-0.\n");
309 rs780_nb_gfx_dev_table(nb_dev, dev);
310 break;
311 case 2: /* bus0, dev2,3, two GFX */
312 case 3:
313 printk(BIOS_INFO, "Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled);
314 set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
315 (dev->enabled ? 0 : 1) << dev_ind);
316 if (dev->enabled)
317 rs780_gfx_init(nb_dev, dev, dev_ind);
318 break;
319 case 4: /* bus0, dev4-7, four GPPSB */
320 case 5:
321 case 6:
322 case 7:
323 printk(BIOS_INFO, "Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n",
324 dev->enabled);
325 set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
326 (dev->enabled ? 0 : 1) << dev_ind);
327 if (dev->enabled)
328 rs780_gpp_sb_init(nb_dev, dev, dev_ind);
329 break;
330 case 8: /* bus0, dev8, SB */
331 printk(BIOS_INFO, "Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled);
332 set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6,
333 (dev->enabled ? 1 : 0) << 6);
334 if (dev->enabled)
335 rs780_gpp_sb_init(nb_dev, dev, dev_ind);
336 break;
337 case 9: /* bus 0, dev 9,10, GPP */
338 case 10:
339 printk(BIOS_INFO, "Bus-0, Dev-9, 10, Fun-0. enable=%d\n",
340 dev->enabled);
341 set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind),
342 (dev->enabled ? 0 : 1) << (7 + dev_ind));
343 if (dev->enabled)
344 rs780_gpp_sb_init(nb_dev, dev, dev_ind);
345
346 if (dev_ind == 10) {
347 disable_pcie_bar3(nb_dev);
348 pcie_hide_unused_ports(nb_dev);
349 }
350 break;
351 default:
352 printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev));
353 }
354 }
355
356 struct chip_operations southbridge_amd_rs780_ops = {
357 CHIP_NAME("ATI RS780")
358 .enable_dev = rs780_enable,
359 };
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