src/southbridge/amd/cimx/sb800/chip.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc.
  18  */
  19
  20 #ifndef _CIMX_SB800_CHIP_H_
  21 #define _CIMX_SB800_CHIP_H_
  22 #include "fan.h" /* include for #defines used in devicetree.cb */
  23
  24 /*
  25  * configuration set in mainboard/devicetree.cb
  26  *  boot_switch_sata_ide:
  27  *   0 -set SATA as primary, PATA(IDE) as secondary.
  28  *   1 -set PATA(IDE) as primary, SATA as secondary. if you want to boot from IDE,
  29  *  gpp_configuration - The configuration of General Purpose Port A/B/C/D
  30  *   0(GPP_CFGMODE_X4000) -PortA Lanes[3:0]
  31  *   2(GPP_CFGMODE_X2200) -PortA Lanes[1:0], PortB Lanes[3:2]
  32  *   3(GPP_CFGMODE_X2110) -PortA Lanes[1:0], PortB Lane2, PortC Lane3
  33  *   4(GPP_CFGMODE_X1111) -PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
  34  */
  35 struct southbridge_amd_cimx_sb800_config
  36 {
  37         u32 boot_switch_sata_ide : 1;
  38         u32 disconnect_pcib : 1;
  39         u8  gpp_configuration;
  40
  41         /*
  42          * SB800 IMC and fan control
  43          */
  44
  45         u16 imc_port_address;
  46
  47         u32 fan0_enabled : 1;
  48         u32 fan1_enabled : 1;
  49         u32 fan2_enabled : 1;
  50         u32 fan3_enabled : 1;
  51         u32 fan4_enabled : 1;
  52         u32 imc_fan_zone0_enabled : 1;
  53         u32 imc_fan_zone1_enabled : 1;
  54         u32 imc_fan_zone2_enabled : 1;
  55         u32 imc_fan_zone3_enabled : 1;
  56         u32 imc_tempin0_enabled : 1;
  57         u32 imc_tempin1_enabled : 1;
  58         u32 imc_tempin2_enabled : 1;
  59         u32 imc_tempin3_enabled : 1;
  60
  61         union {
  62                 struct {
  63                         u8  fan0_control_reg_value;
  64                         u8  fan0_frequency_reg_value;
  65                         u8  fan0_low_duty_reg_value;
  66                         u8  fan0_med_duty_reg_value;
  67                         u8  fan0_multiplier_reg_value;
  68                         u8  fan0_low_temp_lo_reg_value;
  69                         u8  fan0_low_temp_hi_reg_value;
  70                         u8  fan0_med_temp_lo_reg_value;
  71                         u8  fan0_med_temp_hi_reg_value;
  72                         u8  fan0_high_temp_lo_reg_value;
  73                         u8  fan0_high_temp_hi_reg_value;
  74                         u8  fan0_linear_range_reg_value;
  75                         u8  fan0_linear_hold_reg_value;
  76                 };
  77                 u8  fan0_config_vals[FAN_REGISTER_COUNT];
  78         };
  79
  80         union {
  81                 struct {
  82                         u8  fan1_control_reg_value;
  83                         u8  fan1_frequency_reg_value;
  84                         u8  fan1_low_duty_reg_value;
  85                         u8  fan1_med_duty_reg_value;
  86                         u8  fan1_multiplier_reg_value;
  87                         u8  fan1_low_temp_lo_reg_value;
  88                         u8  fan1_low_temp_hi_reg_value;
  89                         u8  fan1_med_temp_lo_reg_value;
  90                         u8  fan1_med_temp_hi_reg_value;
  91                         u8  fan1_high_temp_lo_reg_value;
  92                         u8  fan1_high_temp_hi_reg_value;
  93                         u8  fan1_linear_range_reg_value;
  94                         u8  fan1_linear_hold_reg_value;
  95                 };
  96                 u8  fan1_config_vals[FAN_REGISTER_COUNT];
  97         };
  98
  99         union {
 100                 struct {
 101                         u8  fan2_control_reg_value;
 102                         u8  fan2_frequency_reg_value;
 103                         u8  fan2_low_duty_reg_value;
 104                         u8  fan2_med_duty_reg_value;
 105                         u8  fan2_multiplier_reg_value;
 106                         u8  fan2_low_temp_lo_reg_value;
 107                         u8  fan2_low_temp_hi_reg_value;
 108                         u8  fan2_med_temp_lo_reg_value;
 109                         u8  fan2_med_temp_hi_reg_value;
 110                         u8  fan2_high_temp_lo_reg_value;
 111                         u8  fan2_high_temp_hi_reg_value;
 112                         u8  fan2_linear_range_reg_value;
 113                         u8  fan2_linear_hold_reg_value;
 114                 };
 115                 u8  fan2_config_vals[FAN_REGISTER_COUNT];
 116         };
 117
 118         union {
 119                 struct {
 120                         u8  fan3_control_reg_value;
 121                         u8  fan3_frequency_reg_value;
 122                         u8  fan3_low_duty_reg_value;
 123                         u8  fan3_med_duty_reg_value;
 124                         u8  fan3_multiplier_reg_value;
 125                         u8  fan3_low_temp_lo_reg_value;
 126                         u8  fan3_low_temp_hi_reg_value;
 127                         u8  fan3_med_temp_lo_reg_value;
 128                         u8  fan3_med_temp_hi_reg_value;
 129                         u8  fan3_high_temp_lo_reg_value;
 130                         u8  fan3_high_temp_hi_reg_value;
 131                         u8  fan3_linear_range_reg_value;
 132                         u8  fan3_linear_hold_reg_value;
 133                 };
 134                 u8  fan3_config_vals[FAN_REGISTER_COUNT];
 135         };
 136
 137         union {
 138                 struct {
 139                         u8  fan4_control_reg_value;
 140                         u8  fan4_frequency_reg_value;
 141                         u8  fan4_low_duty_reg_value;
 142                         u8  fan4_med_duty_reg_value;
 143                         u8  fan4_multiplier_reg_value;
 144                         u8  fan4_low_temp_lo_reg_value;
 145                         u8  fan4_low_temp_hi_reg_value;
 146                         u8  fan4_med_temp_lo_reg_value;
 147                         u8  fan4_med_temp_hi_reg_value;
 148                         u8  fan4_high_temp_lo_reg_value;
 149                         u8  fan4_high_temp_hi_reg_value;
 150                         u8  fan4_linear_range_reg_value;
 151                         u8  fan4_linear_hold_reg_value;
 152                 };
 153                 u8  fan4_config_vals[FAN_REGISTER_COUNT];
 154         };
 155
 156         union {
 157                 struct {
 158                         u8 imc_zone0_mode1;
 159                         u8 imc_zone0_mode2;
 160                         u8 imc_zone0_temp_offset;
 161                         u8 imc_zone0_hysteresis;
 162                         u8 imc_zone0_smbus_addr;
 163                         u8 imc_zone0_smbus_num;
 164                         u8 imc_zone0_pwm_step;
 165                         u8 imc_zone0_ramping;
 166                 };
 167                 u8  imc_zone0_config_vals[IMC_FAN_CONFIG_COUNT];
 168         };
 169         u8  imc_zone0_thresholds[IMC_FAN_THRESHOLD_COUNT];
 170         u8  imc_zone0_fanspeeds[IMC_FAN_SPEED_COUNT];
 171
 172         union {
 173                 struct {
 174                 u8  imc_zone1_mode1;
 175                 u8  imc_zone1_mode2;
 176                 u8  imc_zone1_temp_offset;
 177                 u8  imc_zone1_hysteresis;
 178                 u8  imc_zone1_smbus_addr;
 179                 u8  imc_zone1_smbus_num;
 180                 u8  imc_zone1_pwm_step;
 181                 u8  imc_zone1_ramping;
 182                 };
 183                 u8  imc_zone1_config_vals[IMC_FAN_CONFIG_COUNT];
 184         };
 185         u8  imc_zone1_thresholds[IMC_FAN_THRESHOLD_COUNT];
 186         u8  imc_zone1_fanspeeds[IMC_FAN_SPEED_COUNT];
 187
 188         union {
 189                 struct {
 190                         u8  imc_zone2_mode1;
 191                         u8  imc_zone2_mode2;
 192                         u8  imc_zone2_temp_offset;
 193                         u8  imc_zone2_hysteresis;
 194                         u8  imc_zone2_smbus_addr;
 195                         u8  imc_zone2_smbus_num;
 196                         u8  imc_zone2_pwm_step;
 197                         u8  imc_zone2_ramping;
 198                 };
 199                 u8  imc_zone2_config_vals[IMC_FAN_CONFIG_COUNT];
 200         };
 201         u8  imc_zone2_thresholds[IMC_FAN_THRESHOLD_COUNT];
 202         u8  imc_zone2_fanspeeds[IMC_FAN_SPEED_COUNT];
 203
 204         union {
 205                 struct {
 206                         u8  imc_zone3_mode1;
 207                         u8  imc_zone3_mode2;
 208                         u8  imc_zone3_temp_offset;
 209                         u8  imc_zone3_hysteresis;
 210                         u8  imc_zone3_smbus_addr;
 211                         u8  imc_zone3_smbus_num;
 212                         u8  imc_zone3_pwm_step;
 213                         u8  imc_zone3_ramping;
 214                 };
 215                 u8 imc_zone3_config_vals[IMC_FAN_CONFIG_COUNT];
 216         };
 217         u8  imc_zone3_thresholds[IMC_FAN_THRESHOLD_COUNT];
 218         u8  imc_zone3_fanspeeds[IMC_FAN_SPEED_COUNT];
 219
 220         u32 imc_tempin0_at;
 221         u32 imc_tempin0_ct;
 222         u8 imc_tempin0_tuning_param;
 223
 224         u32 imc_tempin1_at;
 225         u32 imc_tempin1_ct;
 226         u8  imc_tempin1_tuning_param;
 227
 228         u32 imc_tempin2_at;
 229         u32 imc_tempin2_ct;
 230         u8  imc_tempin2_tuning_param;
 231
 232         u32 imc_tempin3_at;
 233         u32 imc_tempin3_ct;
 234         u8  imc_tempin3_tuning_param;
 235
 236 };
 237 #endif /* _CIMX_SB800_CHIP_H_ */