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Remove address from GPLv2 headers
[coreboot.git] / src / soc / samsung / exynos5420 / clock.c
blob6e1420c69b0cc2a2c749fd8926f4a1ebea54e0ff
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2010 Samsung Electronics
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc.
18 */
19
20 #include <arch/io.h>
21 #include <assert.h>
22 #include <console/console.h>
23 #include <soc/clk.h>
24 #include <soc/periph.h>
25 #include <stdlib.h>
26 #include <timer.h>
27
28 /* input clock of PLL: SMDK5420 has 24MHz input clock */
29 #define CONFIG_SYS_CLK_FREQ 24000000
30
31 /* Epll Clock division values to achieve different frequency output */
32 static struct st_epll_con_val epll_div[] = {
33 { 192000000, 0, 48, 3, 1, 0 },
34 { 180000000, 0, 45, 3, 1, 0 },
35 { 73728000, 1, 73, 3, 3, 47710 },
36 { 67737600, 1, 90, 4, 3, 20762 },
37 { 49152000, 0, 49, 3, 3, 9961 },
38 { 45158400, 0, 45, 3, 3, 10381 },
39 { 180633600, 0, 45, 3, 1, 10381 }
40 };
41
42 /* exynos5: return pll clock frequency */
43 unsigned long get_pll_clk(int pllreg)
44 {
45 unsigned long r, m, p, s, k = 0, mask, fout;
46 unsigned int freq;
47
48 switch (pllreg) {
49 case APLL:
50 r = read32(&exynos_clock->apll_con0);
51 break;
52 case MPLL:
53 r = read32(&exynos_clock->mpll_con0);
54 break;
55 case EPLL:
56 r = read32(&exynos_clock->epll_con0);
57 k = read32(&exynos_clock->epll_con1);
58 break;
59 case VPLL:
60 r = read32(&exynos_clock->vpll_con0);
61 k = read32(&exynos_clock->vpll_con1);
62 break;
63 case BPLL:
64 r = read32(&exynos_clock->bpll_con0);
65 break;
66 case RPLL:
67 r = read32(&exynos_clock->rpll_con0);
68 k = read32(&exynos_clock->rpll_con1);
69 break;
70 case SPLL:
71 r = read32(&exynos_clock->spll_con0);
72 break;
73 case CPLL:
74 r = read32(&exynos_clock->cpll_con0);
75 break;
76 case DPLL:
77 r = read32(&exynos_clock->dpll_con0);
78 break;
79 default:
80 printk(BIOS_DEBUG, "Unsupported PLL (%d)\n", pllreg);
81 return 0;
82 }
83
84 /*
85 * APLL_CON: MIDV [25:16]
86 * MPLL_CON: MIDV [25:16]
87 * EPLL_CON: MIDV [24:16]
88 * VPLL_CON: MIDV [24:16]
89 */
90 if (pllreg == APLL || pllreg == BPLL || pllreg == MPLL ||
91 pllreg == SPLL)
92 mask = 0x3ff;
93 else
94 mask = 0x1ff;
95
96 m = (r >> 16) & mask;
97
98 /* PDIV [13:8] */
99 p = (r >> 8) & 0x3f;
100 /* SDIV [2:0] */
101 s = r & 0x7;
102
103 freq = CONFIG_SYS_CLK_FREQ;
104
105 if (pllreg == EPLL || pllreg == RPLL) {
106 k = k & 0xffff;
107 /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
108 fout = (m + k / 65536) * (freq / (p * (1 << s)));
109 } else if (pllreg == VPLL) {
110 k = k & 0xfff;
111 /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
112 fout = (m + k / 1024) * (freq / (p * (1 << s)));
113 } else {
114 /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
115 fout = m * (freq / (p * (1 << s)));
116 }
117
118 return fout;
119 }
120
121 enum peripheral_clock_select {
122 PERIPH_SRC_CPLL = 1,
123 PERIPH_SRC_DPLL = 2,
124 PERIPH_SRC_MPLL = 3,
125 PERIPH_SRC_SPLL = 4,
126 PERIPH_SRC_IPLL = 5,
127 PERIPH_SRC_EPLL = 6,
128 PERIPH_SRC_RPLL = 7,
129 };
130
131 static int clock_select_to_pll(enum peripheral_clock_select sel)
132 {
133 int pll;
134
135 switch (sel) {
136 case PERIPH_SRC_CPLL:
137 pll = CPLL;
138 break;
139 case PERIPH_SRC_DPLL:
140 pll = DPLL;
141 break;
142 case PERIPH_SRC_MPLL:
143 pll = MPLL;
144 break;
145 case PERIPH_SRC_SPLL:
146 pll = SPLL;
147 break;
148 case PERIPH_SRC_IPLL:
149 pll = IPLL;
150 break;
151 case PERIPH_SRC_EPLL:
152 pll = EPLL;
153 break;
154 case PERIPH_SRC_RPLL:
155 pll = RPLL;
156 break;
157 default:
158 pll = -1;
159 break;
160 }
161
162 return pll;
163 }
164
165 unsigned long clock_get_periph_rate(enum periph_id peripheral)
166 {
167 unsigned long sclk;
168 unsigned int src, div;
169
170 switch (peripheral) {
171 case PERIPH_ID_UART0:
172 src = (read32(&exynos_clock->clk_src_peric0) >> 4) & 0x7;
173 div = (read32(&exynos_clock->clk_div_peric0) >> 8) & 0xf;
174 break;
175 case PERIPH_ID_UART1:
176 src = (read32(&exynos_clock->clk_src_peric0) >> 8) & 0x7;
177 div = (read32(&exynos_clock->clk_div_peric0) >> 12) & 0xf;
178 break;
179 case PERIPH_ID_UART2:
180 src = (read32(&exynos_clock->clk_src_peric0) >> 12) & 0x7;
181 div = (read32(&exynos_clock->clk_div_peric0) >> 16) & 0xf;
182 break;
183 case PERIPH_ID_UART3:
184 src = (read32(&exynos_clock->clk_src_peric0) >> 16) & 0x7;
185 div = (read32(&exynos_clock->clk_div_peric0) >> 20) & 0xf;
186 break;
187 case PERIPH_ID_PWM0:
188 case PERIPH_ID_PWM1:
189 case PERIPH_ID_PWM2:
190 case PERIPH_ID_PWM3:
191 case PERIPH_ID_PWM4:
192 src = (read32(&exynos_clock->clk_src_peric0) >> 24) & 0x7;
193 div = (read32(&exynos_clock->clk_div_peric0) >> 28) & 0x7;
194 break;
195 case PERIPH_ID_SPI0:
196 src = (read32(&exynos_clock->clk_src_peric1) >> 20) & 0x7;
197 div = (read32(&exynos_clock->clk_div_peric1) >> 20) & 0xf;
198 break;
199 case PERIPH_ID_SPI1:
200 src = (read32(&exynos_clock->clk_src_peric1) >> 24) & 0x7;
201 div = (read32(&exynos_clock->clk_div_peric1) >> 24) & 0xf;
202 break;
203 case PERIPH_ID_SPI2:
204 src = (read32(&exynos_clock->clk_src_peric1) >> 28) & 0x7;
205 div = (read32(&exynos_clock->clk_div_peric1) >> 28) & 0xf;
206 break;
207 case PERIPH_ID_SPI3: /* aka SPI0_ISP */
208 src = (read32(&exynos_clock->clk_src_isp) >> 16) & 0x7;
209 div = (read32(&exynos_clock->clk_div_isp0) >> 0) & 0x7;
210 break;
211 case PERIPH_ID_SPI4: /* aka SPI1_ISP */
212 src = (read32(&exynos_clock->clk_src_isp) >> 12) & 0x7;
213 div = (read32(&exynos_clock->clk_div_isp1) >> 4) & 0x7;
214 break;
215 case PERIPH_ID_I2C0:
216 case PERIPH_ID_I2C1:
217 case PERIPH_ID_I2C2:
218 case PERIPH_ID_I2C3:
219 case PERIPH_ID_I2C4:
220 case PERIPH_ID_I2C5:
221 case PERIPH_ID_I2C6:
222 case PERIPH_ID_I2C7:
223 case PERIPH_ID_I2C8:
224 case PERIPH_ID_I2C9:
225 case PERIPH_ID_I2C10:
226 /*
227 * I2C block parent clock selection is different from other
228 * peripherals, so we handle it all here.
229 * TODO: Add a helper function like with the peripheral clock
230 * select fields?
231 */
232 src = (read32(&exynos_clock->clk_src_top1) >> 8) & 0x3;
233 if (src == 0x0)
234 src = CPLL;
235 else if (src == 0x1)
236 src = DPLL;
237 else if (src == 0x2)
238 src = MPLL;
239 else
240 return -1;
241
242 sclk = get_pll_clk(src);
243 div = ((read32(&exynos_clock->clk_div_top1) >> 8) & 0x3f) + 1;
244 return sclk / div;
245 default:
246 printk(BIOS_DEBUG, "%s: invalid peripheral %d",
247 __func__, peripheral);
248 return -1;
249 };
250
251 src = clock_select_to_pll(src);
252 if (src < 0) {
253 printk(BIOS_DEBUG, "%s: cannot determine source PLL", __func__);
254 return -1;
255 }
256
257 sclk = get_pll_clk(src);
258
259 return sclk / (div + 1);
260 }
261
262 /* exynos5: return ARM clock frequency */
263 unsigned long get_arm_clk(void)
264 {
265 unsigned long div;
266 unsigned long armclk;
267 unsigned int arm_ratio;
268 unsigned int arm2_ratio;
269
270 div = read32(&exynos_clock->clk_div_cpu0);
271
272 /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
273 arm_ratio = (div >> 0) & 0x7;
274 arm2_ratio = (div >> 28) & 0x7;
275
276 armclk = get_pll_clk(APLL) / (arm_ratio + 1);
277 armclk /= (arm2_ratio + 1);
278
279 return armclk;
280 }
281
282 /* exynos5: get the mmc clock */
283 static unsigned long get_mmc_clk(int dev_index)
284 {
285 unsigned long uclk, sclk;
286 unsigned int sel, ratio;
287 int shift = 0;
288
289 sel = read32(&exynos_clock->clk_src_fsys);
290 sel = (sel >> ((dev_index * 4) + 8)) & 0x7;
291
292 if (sel == 0x3)
293 sclk = get_pll_clk(MPLL);
294 else if (sel == 0x6)
295 sclk = get_pll_clk(EPLL);
296 else
297 return 0;
298
299 ratio = read32(&exynos_clock->clk_div_fsys1);
300
301 shift = dev_index * 10;
302
303 ratio = (ratio >> shift) & 0x3ff;
304 uclk = (sclk / (ratio + 1));
305 printk(BIOS_DEBUG, "%s(%d): %lu\n", __func__, dev_index, uclk);
306
307 return uclk;
308 }
309
310 /* exynos5: set the mmc clock */
311 void set_mmc_clk(int dev_index, unsigned int div)
312 {
313 void *addr;
314 unsigned int val, shift;
315
316 addr = &exynos_clock->clk_div_fsys1;
317 shift = dev_index * 10;
318
319 val = read32(addr);
320 val &= ~(0x3ff << shift);
321 val |= (div & 0x3ff) << shift;
322 write32(addr, val);
323 }
324
325 /* Set DW MMC Controller clock */
326 int clock_set_dwmci(enum periph_id peripheral)
327 {
328 /* Request MMC clock value to 52MHz. */
329 const unsigned long freq = 52000000;
330 unsigned long sdclkin, cclkin;
331 int device_index = (int)peripheral - (int)PERIPH_ID_SDMMC0;
332
333 ASSERT(device_index >= 0 && device_index < 4);
334 sdclkin = get_mmc_clk(device_index);
335 if (!sdclkin) {
336 return -1;
337 }
338
339 /* The SDCLKIN is divided inside the controller by the DIVRATIO field in
340 * CLKSEL register, so we must calculate clock value as
341 * cclk_in = SDCLKIN / (DIVRATIO + 1)
342 * Currently the RIVRATIO must be 3 for MMC0 and MMC2 on Exynos5420
343 * (and must be configured in payload).
344 */
345 if (device_index == 0 || device_index == 2){
346 int divratio = 3;
347 sdclkin /= (divratio + 1);
348 }
349 printk(BIOS_DEBUG, "%s(%d): sdclkin: %ld\n", __func__, device_index, sdclkin);
350
351 cclkin = CEIL_DIV(sdclkin, freq);
352 set_mmc_clk(device_index, cclkin);
353 return 0;
354 }
355
356 void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor)
357 {
358 unsigned shift;
359 unsigned mask = 0xff;
360 u32 *reg;
361
362 /*
363 * For now we only handle a very small subset of peripherals here.
364 * Others will need to (and do) mangle the clock registers
365 * themselves, At some point it is hoped that this function can work
366 * from a table or calculated register offset / mask. For now this
367 * is at least better than spreading clock control code around
368 * U-Boot.
369 */
370 switch (periph_id) {
371 case PERIPH_ID_SPI0:
372 reg = &exynos_clock->clk_div_peric4;
373 shift = 8;
374 break;
375 case PERIPH_ID_SPI1:
376 reg = &exynos_clock->clk_div_peric4;
377 shift = 16;
378 break;
379 case PERIPH_ID_SPI2:
380 reg = &exynos_clock->clk_div_peric4;
381 shift = 24;
382 break;
383 case PERIPH_ID_SPI3:
384 reg = &exynos_clock->clk_div_isp1;
385 shift = 0;
386 break;
387 case PERIPH_ID_SPI4:
388 reg = &exynos_clock->clk_div_isp1;
389 shift = 8;
390 break;
391 default:
392 printk(BIOS_DEBUG, "%s: Unsupported peripheral ID %d\n", __func__,
393 periph_id);
394 return;
395 }
396 clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift);
397 }
398
399 void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor)
400 {
401 unsigned shift;
402 unsigned mask = 0xf;
403 u32 *reg;
404
405 switch (periph_id) {
406 case PERIPH_ID_SPI0:
407 reg = &exynos_clock->clk_div_peric1;
408 shift = 20;
409 break;
410 case PERIPH_ID_SPI1:
411 reg = &exynos_clock->clk_div_peric1;
412 shift = 24;
413 break;
414 case PERIPH_ID_SPI2:
415 reg = &exynos_clock->clk_div_peric1;
416 shift = 28;
417 break;
418 case PERIPH_ID_SPI3:
419 reg = &exynos_clock->clk_div_isp1;
420 shift = 16;
421 break;
422 case PERIPH_ID_SPI4:
423 reg = &exynos_clock->clk_div_isp1;
424 shift = 20;
425 break;
426 default:
427 printk(BIOS_DEBUG, "%s: Unsupported peripheral ID %d\n", __func__,
428 periph_id);
429 return;
430 }
431 clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift);
432 }
433
434 /**
435 * Linearly searches for the most accurate main and fine stage clock scalars
436 * (divisors) for a specified target frequency and scalar bit sizes by checking
437 * all multiples of main_scalar_bits values. Will always return scalars up to or
438 * slower than target.
439 *
440 * @param main_scalar_bits Number of main scalar bits, must be > 0 and < 32
441 * @param fine_scalar_bits Number of fine scalar bits, must be > 0 and < 32
442 * @param input_rate Clock frequency to be scaled in Hz
443 * @param target_rate Desired clock frequency in Hz
444 * @param best_fine_scalar Pointer to store the fine stage divisor
445 *
446 * @return best_main_scalar Main scalar for desired frequency or -1 if none
447 * found
448 */
449 static int clock_calc_best_scalar(unsigned int main_scaler_bits,
450 unsigned int fine_scalar_bits, unsigned int input_rate,
451 unsigned int target_rate, unsigned int *best_fine_scalar)
452 {
453 int i;
454 int best_main_scalar = -1;
455 unsigned int best_error = target_rate;
456 const unsigned int cap = (1 << fine_scalar_bits) - 1;
457 const unsigned int loops = 1 << main_scaler_bits;
458
459 printk(BIOS_DEBUG, "Input Rate is %u, Target is %u, Cap is %u\n", input_rate,
460 target_rate, cap);
461
462 ASSERT(best_fine_scalar != NULL);
463 ASSERT(main_scaler_bits <= fine_scalar_bits);
464
465 *best_fine_scalar = 1;
466
467 if (input_rate == 0 || target_rate == 0)
468 return -1;
469
470 if (target_rate >= input_rate)
471 return 1;
472
473 for (i = 1; i <= loops; i++) {
474 const unsigned int effective_div = MAX(MIN(input_rate / i /
475 target_rate, cap), 1);
476 const unsigned int effective_rate = input_rate / i /
477 effective_div;
478 const int error = target_rate - effective_rate;
479
480 printk(BIOS_DEBUG, "%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div,
481 effective_rate, error);
482
483 if (error >= 0 && error <= best_error) {
484 best_error = error;
485 best_main_scalar = i;
486 *best_fine_scalar = effective_div;
487 }
488 }
489
490 return best_main_scalar;
491 }
492
493 int clock_set_rate(enum periph_id periph_id, unsigned int rate)
494 {
495 int main_scalar;
496 unsigned int fine;
497
498 switch (periph_id) {
499 case PERIPH_ID_SPI0:
500 case PERIPH_ID_SPI1:
501 case PERIPH_ID_SPI2:
502 case PERIPH_ID_SPI3:
503 case PERIPH_ID_SPI4:
504 main_scalar = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
505 if (main_scalar < 0) {
506 printk(BIOS_DEBUG, "%s: Cannot set clock rate for periph %d",
507 __func__, periph_id);
508 return -1;
509 }
510 clock_ll_set_ratio(periph_id, main_scalar - 1);
511 clock_ll_set_pre_ratio(periph_id, fine - 1);
512 break;
513 default:
514 printk(BIOS_DEBUG, "%s: Unsupported peripheral ID %d\n", __func__,
515 periph_id);
516 return -1;
517 }
518
519 return 0;
520 }
521
522 int clock_set_mshci(enum periph_id peripheral)
523 {
524 u32 *addr;
525 unsigned int clock;
526 unsigned int tmp;
527 unsigned int i;
528
529 /* get mpll clock */
530 clock = get_pll_clk(MPLL) / 1000000;
531
532 /*
533 * CLK_DIV_FSYS1
534 * MMC0_PRE_RATIO [15:8], MMC0_RATIO [3:0]
535 * CLK_DIV_FSYS2
536 * MMC2_PRE_RATIO [15:8], MMC2_RATIO [3:0]
537 */
538 switch (peripheral) {
539 case PERIPH_ID_SDMMC0:
540 addr = &exynos_clock->clk_div_fsys1;
541 break;
542 case PERIPH_ID_SDMMC2:
543 addr = &exynos_clock->clk_div_fsys2;
544 break;
545 default:
546 printk(BIOS_DEBUG, "invalid peripheral\n");
547 return -1;
548 }
549 tmp = read32(addr) & ~0xff0f;
550 for (i = 0; i <= 0xf; i++) {
551 if ((clock / (i + 1)) <= 400) {
552 write32(addr, tmp | i << 0);
553 break;
554 }
555 }
556 return 0;
557 }
558
559 int clock_epll_set_rate(unsigned long rate)
560 {
561 unsigned int epll_con, epll_con_k;
562 unsigned int i;
563 unsigned int lockcnt;
564 struct stopwatch sw;
565
566 epll_con = read32(&exynos_clock->epll_con0);
567 epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK <<
568 EPLL_CON0_LOCK_DET_EN_SHIFT) |
569 EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT |
570 EPLL_CON0_PDIV_MASK << EPLL_CON0_PDIV_SHIFT |
571 EPLL_CON0_SDIV_MASK << EPLL_CON0_SDIV_SHIFT);
572
573 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
574 if (epll_div[i].freq_out == rate)
575 break;
576 }
577
578 if (i == ARRAY_SIZE(epll_div))
579 return -1;
580
581 epll_con_k = epll_div[i].k_dsm << 0;
582 epll_con |= epll_div[i].en_lock_det << EPLL_CON0_LOCK_DET_EN_SHIFT;
583 epll_con |= epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT;
584 epll_con |= epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT;
585 epll_con |= epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
586
587 /*
588 * Required period ( in cycles) to generate a stable clock output.
589 * The maximum clock time can be up to 3000 * PDIV cycles of PLLs
590 * frequency input (as per spec)
591 */
592 lockcnt = 3000 * epll_div[i].p_div;
593
594 write32(&exynos_clock->epll_lock, lockcnt);
595 write32(&exynos_clock->epll_con0, epll_con);
596 write32(&exynos_clock->epll_con1, epll_con_k);
597
598 stopwatch_init_msecs_expire(&sw, TIMEOUT_EPLL_LOCK);
599
600 while (!(read32(&exynos_clock->epll_con0) &
601 (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) {
602 if (stopwatch_expired(&sw)) {
603 printk(BIOS_DEBUG, "%s: Timeout waiting for EPLL lock\n", __func__);
604 return -1;
605 }
606 }
607
608 return 0;
609 }
610
611 void clock_select_i2s_clk_source(void)
612 {
613 clrsetbits_le32(&exynos_clock->clk_src_peric1, AUDIO1_SEL_MASK,
614 (CLK_SRC_SCLK_EPLL));
615 }
616
617 int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq)
618 {
619 unsigned int div ;
620
621 if ((dst_frq == 0) || (src_frq == 0)) {
622 printk(BIOS_DEBUG, "%s: Invalid frequency input for prescaler\n", __func__);
623 printk(BIOS_DEBUG, "src frq = %d des frq = %d ", src_frq, dst_frq);
624 return -1;
625 }
626
627 div = (src_frq / dst_frq);
628 if (div > AUDIO_1_RATIO_MASK) {
629 printk(BIOS_DEBUG, "%s: Frequency ratio is out of range\n", __func__);
630 printk(BIOS_DEBUG, "src frq = %d des frq = %d ", src_frq, dst_frq);
631 return -1;
632 }
633 clrsetbits_le32(&exynos_clock->clk_div_peric4, AUDIO_1_RATIO_MASK,
634 (div & AUDIO_1_RATIO_MASK));
635 return 0;
636 }
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