src/soc/nvidia/tegra132/uart.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2009 Samsung Electronics
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc.
  18  */
  19
  20 #include <arch/io.h>
  21 #include <boot/coreboot_tables.h>
  22 #include <console/console.h>    /* for __console definition */
  23 #include <console/uart.h>
  24 #include <drivers/uart/uart8250reg.h>
  25 #include <stdint.h>
  26
  27 /*
  28  * TODO: Use DRIVERS_UART_8250MEM driver instead.
  29  * There is an issue in the IO call functions where x86 and ARM
  30  * ordering is reversed. This 8250MEM driver uses the x86 convention.
  31  * This driver can be replaced once the IO calls are sorted.
  32  */
  33 struct tegra132_uart {
  34         union {
  35                 uint32_t thr; // Transmit holding register.
  36                 uint32_t rbr; // Receive buffer register.
  37                 uint32_t dll; // Divisor latch lsb.
  38         };
  39         union {
  40                 uint32_t ier; // Interrupt enable register.
  41                 uint32_t dlm; // Divisor latch msb.
  42         };
  43         union {
  44                 uint32_t iir; // Interrupt identification register.
  45                 uint32_t fcr; // FIFO control register.
  46         };
  47         uint32_t lcr; // Line control register.
  48         uint32_t mcr; // Modem control register.
  49         uint32_t lsr; // Line status register.
  50         uint32_t msr; // Modem status register.
  51 } __attribute__ ((packed));
  52
  53 static void tegra132_uart_tx_flush(struct tegra132_uart *uart_ptr);
  54 static int tegra132_uart_tst_byte(struct tegra132_uart *uart_ptr);
  55
  56 static void tegra132_uart_init(struct tegra132_uart *uart_ptr)
  57 {
  58         const uint8_t line_config = UART8250_LCR_WLS_8; // 8n1
  59
  60         uint16_t divisor = (u16) uart_baudrate_divisor(default_baudrate(),
  61                 uart_platform_refclk(), 16);
  62
  63         tegra132_uart_tx_flush(uart_ptr);
  64
  65         // Disable interrupts.
  66         write8(&uart_ptr->ier, 0);
  67         // Force DTR and RTS to high.
  68         write8(&uart_ptr->mcr, UART8250_MCR_DTR | UART8250_MCR_RTS);
  69         // Set line configuration, access divisor latches.
  70         write8(&uart_ptr->lcr, UART8250_LCR_DLAB | line_config);
  71         // Set the divisor.
  72         write8(&uart_ptr->dll, divisor & 0xff);
  73         write8(&uart_ptr->dlm, (divisor >> 8) & 0xff);
  74         // Hide the divisor latches.
  75         write8(&uart_ptr->lcr, line_config);
  76         // Enable FIFOs, and clear receive and transmit.
  77         write8(&uart_ptr->fcr, UART8250_FCR_FIFO_EN |
  78                UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT);
  79 }
  80
  81 static unsigned char tegra132_uart_rx_byte(struct tegra132_uart *uart_ptr)
  82 {
  83         if (!tegra132_uart_tst_byte(uart_ptr))
  84                 return 0;
  85         return read8(&uart_ptr->rbr);
  86 }
  87
  88 static void tegra132_uart_tx_byte(struct tegra132_uart *uart_ptr, unsigned char data)
  89 {
  90         while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE));
  91         write8(&uart_ptr->thr, data);
  92 }
  93
  94 static void tegra132_uart_tx_flush(struct tegra132_uart *uart_ptr)
  95 {
  96         while (!(read8(&uart_ptr->lsr) & UART8250_LSR_TEMT));
  97 }
  98
  99 static int tegra132_uart_tst_byte(struct tegra132_uart *uart_ptr)
 100 {
 101         return (read8(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR;
 102 }
 103
 104 /* FIXME: Add mainboard override */
 105 unsigned int uart_platform_refclk(void)
 106 {
 107         return 408000000;
 108 }
 109
 110 uintptr_t uart_platform_base(int idx)
 111 {
 112         /* Default to UART A */
 113         unsigned int base = 0x70006000;
 114         /* UARTs A - E are mapped as index 0 - 4 */
 115         if ((idx < 5) && (idx >= 0)) {
 116                 if (idx != 1) { /* Not UART B */
 117                         base += idx * 0x100;
 118                 } else {
 119                         base += 0x40;
 120                 }
 121         }
 122         return base;
 123 }
 124
 125 void uart_init(int idx)
 126 {
 127         struct tegra132_uart *uart_ptr = uart_platform_baseptr(idx);
 128         tegra132_uart_init(uart_ptr);
 129 }
 130
 131 unsigned char uart_rx_byte(int idx)
 132 {
 133         struct tegra132_uart *uart_ptr = uart_platform_baseptr(idx);
 134         return tegra132_uart_rx_byte(uart_ptr);
 135 }
 136
 137 void uart_tx_byte(int idx, unsigned char data)
 138 {
 139         struct tegra132_uart *uart_ptr = uart_platform_baseptr(idx);
 140         tegra132_uart_tx_byte(uart_ptr, data);
 141 }
 142
 143 void uart_tx_flush(int idx)
 144 {
 145         struct tegra132_uart *uart_ptr = uart_platform_baseptr(idx);
 146         tegra132_uart_tx_flush(uart_ptr);
 147 }
 148
 149 #if ENV_RAMSTAGE
 150 void uart_fill_lb(void *data)
 151 {
 152         struct lb_serial serial;
 153         serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
 154         serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
 155         serial.baud = default_baudrate();
 156         serial.regwidth = 1;
 157         lb_add_serial(&serial, data);
 158
 159         lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
 160 }
 161 #endif