src/northbridge/amd/amdfam10/util.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Vincent Legoll <vincent.legoll@gmail.com>
   5  * Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.
  19  */
  20
  21 /*
  22  * fam10 northbridge utilities (dump routing registers).
  23  * Designed to be called at any time.
  24  * It can be called before RAM is set up by including this file.
  25  * It can be called after RAM is set up by including amdfam10.h and enabling the
  26  * compilation of this file in src/northbridge/amd/amdfam10/Makefile.inc.
  27  */
  28 #ifndef __PRE_RAM__
  29 #include <console/console.h>
  30 #include <device/pci.h>
  31 #include <device/pci_ops.h>
  32 #endif
  33 #include "amdfam10.h"
  34
  35 /* Function 1 */
  36 /* the DRAM, MMIO,and PCIIO routing are 64-bit registers, hence the ending at
  37  * 0x78, 0xb8, and 0xd8
  38  */
  39 #define DRAM_ROUTE_START        0x40
  40 #define DRAM_ROUTE_END          0x78
  41 #define MMIO_ROUTE_START        0x80
  42 #define MMIO_ROUTE_END          0xb8
  43 #define PCIIO_ROUTE_START       0xc0
  44 #define PCIIO_ROUTE_END         0xd8
  45 #define CONFIG_ROUTE_START      0xe0
  46 #define CONFIG_ROUTE_END        0xec
  47
  48 #define PCI_IO_BASE0            0xc0
  49 #define PCI_IO_BASE1            0xc8
  50 #define PCI_IO_BASE2            0xd0
  51 #define PCI_IO_BASE3            0xd8
  52 #define PCI_IO_BASE_VGA_EN      (1 << 4)
  53 #define PCI_IO_BASE_NO_ISA      (1 << 5)
  54
  55 #define BITS(r, shift, mask) (((r>>shift)&mask))
  56
  57 /**
  58  * Return "R" if the register has read-enable bit set.
  59  */
  60 static const char *re(u32 i)
  61 {
  62         return ((i & 1) ? "R" : "");
  63 }
  64
  65 /**
  66  * Return "W" if the register has write-enable bit set.
  67  */
  68 static const char *we(u32 i)
  69 {
  70         return ((i & 1) ? "W" : "");
  71 }
  72
  73 /**
  74  * Return a string containing the interleave settings.
  75  */
  76 static const char *ileave(u32 base)
  77 {
  78         switch ((base >> 8) & 7) {
  79         case 0:
  80                 return "No interleave";
  81         case 1:
  82                 return "2 nodes";
  83         case 3:
  84                 return "4 nodes";
  85         case 7:
  86                 return "8 nodes";
  87         default:
  88                 return "Reserved";
  89         }
  90 }
  91
  92 /**
  93  * Return the node number.
  94  * For one case (config registers) these are not the right bit fields.
  95  */
  96 static int r_node(u32 reg)
  97 {
  98         return BITS(reg, 0, 0x7);
  99 }
 100
 101 /**
 102  * Return the link number.
 103  * For one case (config registers) these are not the right bit fields.
 104  */
 105 static int r_link(u32 reg)
 106 {
 107         return BITS(reg, 4, 0x3);
 108 }
 109
 110 /**
 111  * Print the DRAM routing info for one base/limit pair.
 112  *
 113  * Show base, limit, dest node, dest link on that node, read and write
 114  * enable, and interleave information.
 115  *
 116  * @param level Printing level
 117  * @param which Register number
 118  * @param base Base register
 119  * @param lim Limit register
 120  */
 121 static void showdram(int level, u8 which, u32 base, u32 lim)
 122 {
 123         printk(level, "DRAM(%02x)%010llx-%010llx, ->(%d), %s, %s, %s, %d\n",
 124                which, (((u64) base & 0xffff0000) << 8),
 125                (((u64) lim & 0xffff0000) << 8) + 0xffffff,
 126                r_node(lim), re(base), we(base), ileave(base), (lim >> 8) & 3);
 127 }
 128
 129 /**
 130  * Print the config routing info for a config register.
 131  *
 132  * Show base, limit, dest node, dest link on that node, read and write
 133  * enable, and device number compare enable
 134  *
 135  * @param level Printing level
 136  * @param which Register number
 137  * @param reg Config register
 138  */
 139 static void showconfig(int level, u8 which, u32 reg)
 140 {
 141         /* Don't use r_node() and r_link() here. */
 142         printk(level, "CONFIG(%02x)%02x-%02x ->(%d,%d),%s %s (%s numbers)\n",
 143                which, BITS(reg, 16, 0xff), BITS(reg, 24, 0xff),
 144                BITS(reg, 4, 0x7), BITS(reg, 8, 0x3),
 145                re(reg), we(reg),
 146                BITS(reg, 2, 0x1)?"dev":"bus");
 147 }
 148
 149 /**
 150  * Print the PCIIO routing info for one base/limit pair.
 151  *
 152  * Show base, limit, dest node, dest link on that node, read and write
 153  * enable, and VGA and ISA Enable.
 154  *
 155  * @param level Printing level
 156  * @param which Register number
 157  * @param base Base register
 158  * @param lim Limit register
 159  */
 160 static void showpciio(int level, u8 which, u32 base, u32 lim)
 161 {
 162         printk(level, "PCIIO(%02x)%07x-%07x, ->(%d,%d), %s, %s,VGA %d ISA %d\n",
 163                which, BITS(base, 12, 0x3fff) << 12,
 164                (BITS(lim, 12, 0x3fff) << 12) + 0xfff, r_node(lim), r_link(lim),
 165                re(base), we(base), BITS(base, 4, 0x1), BITS(base, 5, 0x1));
 166 }
 167
 168 /**
 169  * Print the MMIO routing info for one base/limit pair.
 170  *
 171  * Show base, limit, dest node, dest link on that node, read and write
 172  * enable, and CPU Disable, Lock, and Non-posted.
 173  *
 174  * @param level Printing level
 175  * @param which Register number
 176  * @param base Base register
 177  * @param lim Limit register
 178  */
 179 static void showmmio(int level, u8 which, u32 base, u32 lim)
 180 {
 181         printk(level, "MMIO(%02x)%010llx-%010llx, ->(%d,%d), %s, %s, "
 182                "CPU disable %d, Lock %d, Non posted %d\n",
 183                which, ((u64) BITS(base, 0, 0xffffff00)) << 8,
 184                (((u64) BITS(lim, 0, 0xffffff00)) << 8) + 0xffff, r_node(lim),
 185                r_link(lim), re(base), we(base), BITS(base, 4, 0x1),
 186                BITS(base, 7, 0x1), BITS(lim, 7, 0x1));
 187 }
 188
 189 /**
 190  * Show all DRAM routing registers. This function is callable at any time.
 191  *
 192  * @param level The debug level.
 193  * @param dev A 32-bit number in the standard bus/dev/fn format which is used
 194  *            raw config space.
 195  */
 196 static void showalldram(int level, device_t dev)
 197 {
 198         u8 reg;
 199         for (reg = DRAM_ROUTE_START; reg <= DRAM_ROUTE_END; reg += 8) {
 200                 u32 base = pci_read_config32(dev, reg);
 201                 u32 lim = pci_read_config32(dev, reg + 4);
 202                 if (base || lim!=(reg-DRAM_ROUTE_START)/8)
 203                         showdram(level, reg, base, lim);
 204         }
 205 }
 206
 207 /**
 208  * Show all MMIO routing registers. This function is callable at any time.
 209  *
 210  * @param level The debug level.
 211  * @param dev A 32-bit number in the standard bus/dev/fn format which is used
 212  *            raw config space.
 213  */
 214 static void showallmmio(int level, device_t dev)
 215 {
 216         u8 reg;
 217         for (reg = MMIO_ROUTE_START; reg <= MMIO_ROUTE_END; reg += 8) {
 218                 u32 base = pci_read_config32(dev, reg);
 219                 u32 lim = pci_read_config32(dev, reg + 4);
 220                 if (base || lim)
 221                         showmmio(level, reg, base, lim);
 222         }
 223 }
 224
 225 /**
 226  * Show all PCIIO routing registers. This function is callable at any time.
 227  *
 228  * @param level The debug level.
 229  * @param dev A 32-bit number in the standard bus/dev/fn format which is used
 230  *            raw config space.
 231  */
 232 static void showallpciio(int level, device_t dev)
 233 {
 234         u8 reg;
 235         for (reg = PCIIO_ROUTE_START; reg <= PCIIO_ROUTE_END; reg += 8) {
 236                 u32 base = pci_read_config32(dev, reg);
 237                 u32 lim = pci_read_config32(dev, reg + 4);
 238                 if (base || lim)
 239                         showpciio(level, reg, base, lim);
 240         }
 241 }
 242
 243 /**
 244  * Show all config routing registers. This function is callable at any time.
 245  *
 246  * @param level The debug level.
 247  * @param dev A 32-bit number in the standard bus/dev/fn format which is used
 248  *            raw config space.
 249  */
 250 static void showallconfig(int level, device_t dev)
 251 {
 252         u8 reg;
 253         for (reg = CONFIG_ROUTE_START; reg <= CONFIG_ROUTE_END; reg += 4) {
 254                 u32 val = pci_read_config32(dev, reg);
 255                 if (val)
 256                         showconfig(level, reg, val);
 257         }
 258 }
 259
 260 /**
 261  * Show all routing registers. This function is callable at any time.
 262  *
 263  * @param level The debug level.
 264  * @param dev A 32-bit number in the standard bus/dev/fn format which is used
 265  *            raw config space.
 266  */
 267 void showallroutes(int level, device_t dev)
 268 {
 269         showalldram(level, dev);
 270         showallmmio(level, dev);
 271         showallpciio(level, dev);
 272         showallconfig(level, dev);
 273 }