src/mainboard/samsung/stumpy/dsdt.asl

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.
  19  */
  20
  21 DefinitionBlock(
  22         "dsdt.aml",
  23         "DSDT",
  24         0x02,           // DSDT revision: ACPI v2.0
  25         "COREv4",       // OEM id
  26         "COREBOOT",     // OEM table id
  27         0x20110725      // OEM revision
  28 )
  29 {
  30         // Some generic macros
  31         #include "acpi/platform.asl"
  32         #include "acpi/mainboard.asl"
  33
  34         // global NVS and variables
  35         #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
  36
  37         // General Purpose Events
  38         //#include "acpi/gpe.asl"
  39
  40         #include "acpi/thermal.asl"
  41
  42         #include <cpu/intel/model_206ax/acpi/cpu.asl>
  43
  44         Scope (\_SB) {
  45                 Device (PCI0)
  46                 {
  47                         #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
  48                         #include <southbridge/intel/bd82x6x/acpi/pch.asl>
  49                 }
  50         }
  51
  52         #include "acpi/chromeos.asl"
  53         #include <vendorcode/google/chromeos/acpi/chromeos.asl>
  54
  55         /* Chipset specific sleep states */
  56         #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
  57 }