src/mainboard/roda/rk9/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 secunet Security Networks AG
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.
  19  */
  20
  21 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
  22
  23 #include <stdint.h>
  24 #include <string.h>
  25 #include <arch/io.h>
  26 #include <cpu/x86/lapic.h>
  27 #include <cpu/x86/msr.h>
  28 #include <cpu/x86/tsc.h>
  29 #include <arch/acpi.h>
  30 #include <cbmem.h>
  31 #include <lib.h>
  32 #include <pc80/mc146818rtc.h>
  33 #include <console/console.h>
  34 #include <southbridge/intel/i82801ix/i82801ix.h>
  35 #include <northbridge/intel/gm45/gm45.h>
  36 #include <superio/smsc/lpc47n227/early_serial.c>
  37
  38 #define LPC_DEV PCI_DEV(0, 0x1f, 0)
  39 #define SERIAL_DEV PNP_DEV(0x2e, LPC47N227_SP1)
  40
  41 static void default_southbridge_gpio_setup(void)
  42 {
  43         /* Enable GPIOs [31:0]. */
  44         outl(0x197e7dfe, DEFAULT_GPIOBASE + 0x00);
  45         /* Set input/output mode [31:0] (0 == out, 1 == in). */
  46         outl(0xe0ea43fe, DEFAULT_GPIOBASE + 0x04);
  47         /* Set gpio levels [31:0]. orig: 0x01140800 (~SATA0, ~SATA1, GSM, BT,
  48                                                      WLAN, ~ANTMUX, ~GPIO12,
  49                                                      ~SUSPWR, SMBALERT) */
  50         outl(0x00000800, DEFAULT_GPIOBASE + 0x0c);
  51
  52         /* Disable blink [31:0]. */
  53         outl(0x00000000, DEFAULT_GPIOBASE + 0x18);
  54         /* Set input inversion [31:0]. */
  55         outl(0x00000182, DEFAULT_GPIOBASE + 0x2c);
  56
  57         /* Enable GPIOs [60:32]. */
  58         outl(0x130300fe, DEFAULT_GPIOBASE + 0x30);
  59         /* Set input/output mode [60:32] (0 == out, 1 == in). */
  60         outl(0x0e55ffb0, DEFAULT_GPIOBASE + 0x34);
  61         /* Set gpio levels [60:32]. orig: 0x10020046 (LNKALERT, ~ATAIO,
  62                                                       DMITERM, TXT, ~CLKSATA,
  63                                                       GPS, AUDIO)  */
  64         outl(0x10020042, DEFAULT_GPIOBASE + 0x38);
  65 }
  66
  67 static void early_lpc_setup(void)
  68 {
  69         /* Set up SuperIO LPC forwards */
  70
  71         /* Configure serial IRQs.*/
  72         pci_write_config8(LPC_DEV, D31F0_SERIRQ_CNTL, 0xd0);
  73         /* Map COMa on 0x3f8, COMb on 0x2f8. */
  74         pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
  75         /* Enable COMa, COMb, Kbd, SuperIO at 0x2e, MCs at 0x4e and 0x62/66. */
  76         pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3c03);
  77 }
  78
  79 static void default_superio_gpio_setup(void)
  80 {
  81         /* Original settings:
  82            idx 30 31 32 33 34 35 36 37  38 39
  83            val 60 00 00 40 00 ff 00 e0  00 80
  84            def 00 00 00 00 00 00 00 00  00 80
  85
  86            Values:
  87            GP1 GP2 GP3 GP4
  88             fd  17  88  14
  89         */
  90         const device_t sio = PNP_DEV(0x2e, 0);
  91
  92         /* Enter super-io's configuration state. */
  93         pnp_enter_conf_state(sio);
  94
  95         /* Set lpc47n227's runtime register block's base address. */
  96         pnp_write_config(sio, 0x30, 0x600 >> 4);
  97
  98         /* Set GP23 to alternate function. */
  99         pnp_write_config(sio, 0x33, 0x40);
 100
 101         /* Set GP30 - GP37 to output mode: COM control */
 102         pnp_write_config(sio, 0x35, 0xff);
 103
 104         /* Set GP45 - GP47 to output mode. */
 105         pnp_write_config(sio, 0x37, 0xe0);
 106
 107         /* Set nIO_PME to open drain. */
 108         pnp_write_config(sio, 0x39, 0x80);
 109
 110         /* Exit configuration state. */
 111         pnp_exit_conf_state(sio);
 112
 113
 114         /* Enable decoding of 0x600-0x60f through lpc. */
 115         pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x000c0601);
 116
 117         /* Set GPIO output values: */
 118         outb(0x88, 0x600 + 0xb + 3); /* GP30 - GP37 */
 119         outb(0x10, 0x600 + 0xb + 4); /* GP40 - GP47 */
 120 }
 121
 122 #include <cpu/intel/romstage.h>
 123 void main(unsigned long bist)
 124 {
 125         sysinfo_t sysinfo;
 126         int s3resume = 0;
 127         int cbmem_initted;
 128         u16 reg16;
 129
 130         /* basic northbridge setup, including MMCONF BAR */
 131         gm45_early_init();
 132
 133         if (bist == 0)
 134                 enable_lapic();
 135
 136         /* First, run everything needed for console output. */
 137         i82801ix_early_init();
 138         early_lpc_setup();
 139         default_superio_gpio_setup();
 140         lpc47n227_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 141         console_init();
 142         printk(BIOS_DEBUG, "running main(bist = %lu)\n", bist);
 143
 144         reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3);
 145         pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16);
 146         if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) {
 147                 printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
 148                 gm45_early_reset();
 149         }
 150
 151         default_southbridge_gpio_setup();
 152
 153         /* ASPM related setting, set early by original BIOS. */
 154         DMIBAR16(0x204) &= ~(3 << 10);
 155
 156         /* Check for S3 resume. */
 157         const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04);
 158         if (((pm1_cnt >> 10) & 7) == 5) {
 159                 if (acpi_s3_resume_allowed()) {
 160                         printk(BIOS_DEBUG, "Resume from S3 detected.\n");
 161                         s3resume = 1;
 162                         /* Clear SLP_TYPE. This will break stage2 but
 163                          * we care for that when we get there.
 164                          */
 165                         outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04);
 166                 } else {
 167                         printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
 168                 }
 169         }
 170
 171         /* RAM initialization */
 172         enter_raminit_or_reset();
 173         memset(&sysinfo, 0, sizeof(sysinfo));
 174         get_gmch_info(&sysinfo);
 175         sysinfo.spd_map[0] = 0x50;
 176         sysinfo.spd_map[1] = 0;
 177         sysinfo.spd_map[2] = 0x52;
 178         sysinfo.spd_map[3] = 0;
 179         sysinfo.enable_igd = 1;
 180         sysinfo.enable_peg = 0;
 181         raminit(&sysinfo, s3resume);
 182
 183         init_pm(&sysinfo, 1);
 184
 185         i82801ix_dmi_setup();
 186         gm45_late_init(sysinfo.stepping);
 187         i82801ix_dmi_poll_vc1();
 188
 189         MCHBAR16(SSKPD_MCHBAR) = 0xCAFE;
 190
 191         init_iommu();
 192
 193         cbmem_initted = !cbmem_recovery(0);
 194 #if CONFIG_HAVE_ACPI_RESUME
 195         /* If there is no high memory area, we didn't boot before, so
 196          * this is not a resume. In that case we just create the cbmem toc.
 197          */
 198         if (s3resume && cbmem_initted) {
 199                 void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
 200
 201                 /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
 202                  * through stage 2. We could keep stuff like stack and heap in high tables
 203                  * memory completely, but that's a wonderful clean up task for another
 204                  * day.
 205                  */
 206                 if (resume_backup_memory)
 207                         memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
 208
 209                 /* Magic for S3 resume */
 210                 pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC);
 211         } else {
 212                 /* Magic for S3 resume */
 213                 pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_NORMAL_BOOT_MAGIC);
 214         }
 215 #endif
 216         printk(BIOS_SPEW, "exit main()\n");
 217 }