src/mainboard/rca/rm4100/gpio.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.
  19  */
  20
  21 #define PME_DEV                 PNP_DEV(0x2e, 0x0a)
  22 #define PME_IO_BASE_ADDR        0x800      /* Runtime register base address */
  23 #define ICH_IO_BASE_ADDR        0x00000500 /* GPIO base address register */
  24
  25 /* Early mainboard specific GPIO setup. */
  26 static void mb_gpio_init(void)
  27 {
  28         device_t dev;
  29         uint16_t port;
  30         uint32_t set_gpio;
  31
  32         /* Southbridge GPIOs. */
  33         /* Set the LPC device statically. */
  34         dev = PCI_DEV(0x0, 0x1f, 0x0);
  35
  36         /* Set the value for GPIO base address register and enable GPIO. */
  37         pci_write_config32(dev, GPIO_BASE, (ICH_IO_BASE_ADDR | 1));
  38         pci_write_config8(dev, GPIO_CNTL, 0x10);
  39
  40         /* Set GPIO23 to high, this enables the LAN controller. */
  41         udelay(10);
  42         set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c);
  43         set_gpio |= 1 << 23;
  44         outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
  45
  46         /* Super I/O GPIOs. */
  47         dev = PME_DEV;
  48         port = dev >> 8;
  49
  50         /* Enter the configuration state. */
  51         outb(0x55, port);
  52         pnp_set_logical_device(dev);
  53         pnp_set_enable(dev, 0);
  54         pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
  55         pnp_set_enable(dev, 1);
  56
  57         /* GP21 - LED_RED */
  58         outl(0x01, PME_IO_BASE_ADDR + 0x2c);
  59
  60         /* GP30 - FAN2_TACH */
  61         outl(0x05, PME_IO_BASE_ADDR + 0x33);
  62
  63         /* GP31 - FAN1_TACH */
  64         outl(0x05, PME_IO_BASE_ADDR + 0x34);
  65
  66         /* GP32 - FAN2_CTRL */
  67         outl(0x04, PME_IO_BASE_ADDR + 0x35);
  68
  69         /* GP33 - FAN1_CTRL */
  70         outl(0x04, PME_IO_BASE_ADDR + 0x36);
  71
  72         /* GP34 - AUD_MUTE_OUT_R */
  73         outl(0x00, PME_IO_BASE_ADDR + 0x37);
  74
  75         /* GP36 - KBRST */
  76         outl(0x00, PME_IO_BASE_ADDR + 0x39);
  77
  78         /* GP37 - A20GATE */
  79         outl(0x00, PME_IO_BASE_ADDR + 0x3a);
  80
  81         /* GP42 - GPIO_PME_OUT */
  82         outl(0x00, PME_IO_BASE_ADDR + 0x3d);
  83
  84         /* GP50 - SER2_RI */
  85         outl(0x05, PME_IO_BASE_ADDR + 0x3f);
  86
  87         /* GP51 - SER2_DCD */
  88         outl(0x05, PME_IO_BASE_ADDR + 0x40);
  89
  90         /* GP52 - SER2_RX */
  91         outl(0x05, PME_IO_BASE_ADDR + 0x41);
  92
  93         /* GP53 - SER2_TX */
  94         outl(0x04, PME_IO_BASE_ADDR + 0x42);
  95
  96         /* GP55 - SER2_RTS */
  97         outl(0x04, PME_IO_BASE_ADDR + 0x44);
  98
  99         /* GP56 - SER2_CTS */
 100         outl(0x05, PME_IO_BASE_ADDR + 0x45);
 101
 102         /* GP57 - SER2_DTR */
 103         outl(0x04, PME_IO_BASE_ADDR + 0x46);
 104
 105         /* GP60 - LED_GREEN */
 106         outl(0x01, PME_IO_BASE_ADDR + 0x47);
 107
 108         /* GP61 - LED_YELLOW */
 109         outl(0x01, PME_IO_BASE_ADDR + 0x48);
 110
 111         /* GP3 */
 112         outl(0xc0, PME_IO_BASE_ADDR + 0x4d);
 113
 114         /* GP4 */
 115         outl(0x04, PME_IO_BASE_ADDR + 0x4e);
 116
 117         /* FAN1 */
 118         outl(0x01, PME_IO_BASE_ADDR + 0x56);
 119
 120         /* FAN2 */
 121         outl(0x01, PME_IO_BASE_ADDR + 0x57);
 122
 123         /* Fan Control */
 124         outl(0x50, PME_IO_BASE_ADDR + 0x58);
 125
 126         /* Fan1 Tachometer */
 127         outl(0xff, PME_IO_BASE_ADDR + 0x59);
 128
 129         /* Fan2 Tachometer */
 130         outl(0xff, PME_IO_BASE_ADDR + 0x5a);
 131
 132         /* LED1 */
 133         outl(0x00, PME_IO_BASE_ADDR + 0x5d);
 134
 135         /* LED2 */
 136         outl(0x00, PME_IO_BASE_ADDR + 0x5e);
 137
 138         /* Keyboard Scan Code */
 139         outl(0x00, PME_IO_BASE_ADDR + 0x5f);
 140
 141         /* Exit the configuration state. */
 142         outb(0xaa, port);
 143 }