2 * This file is part of the coreboot project.
4 * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
5 * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
22 * ISA portions taken from QEMU acpi-dsdt.dsl.
25 DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1)
27 #include "northbridge/amd/amdk8/util.asl"
29 /* For now only define 2 power states:
30 * - S0 which is fully on
31 * - S5 which is soft off
32 * Any others would involve declaring the wake up methods.
34 Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
35 Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 })
38 Method (_PIC, 1, Serialized) {
42 /* Root of the bus hierarchy */
45 /* Top PCI device (CK804) */
48 Name (_HID, EisaId ("PNP0A03"))
62 Method (_CRS, 0, NotSerialized)
64 Name (BUF0, ResourceTemplate ()
67 0x0CF8, // Address Range Minimum
68 0x0CF8, // Address Range Maximum
69 0x01, // Address Alignment
70 0x08, // Address Length
72 WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
73 0x0000, // Address Space Granularity
74 0x0000, // Address Range Minimum
75 0x0CF7, // Address Range Maximum
76 0x0000, // Address Translation Offset
77 0x0CF8, // Address Length
80 /* Methods bellow use SSDT to get actual MMIO regs
81 The IO ports are from 0xd00, optionally an VGA,
82 otherwise the info from MMIO is used.
85 Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
86 Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
87 Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
91 #include "southbridge/nvidia/ck804/acpi/ck804.asl"
93 /* PCI Routing Table */
94 Name (_PRT, Package () {
95 Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LLAS, 0x00 },
96 Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LLAS, 0x00 },
97 Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LUOH, 0x00 },
98 Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LUEH, 0x00 },
99 Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LAUD, 0x00 },
100 Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LMOD, 0x00 },
101 Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LPA0, 0x00 },
102 Package (0x04) { 0x0007FFFF, 0x00, \_SB.PCI0.LSA0, 0x00 },
103 Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LSA1, 0x00 },
105 Package (0x04) { 0x0009FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
106 Package (0x04) { 0x0009FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
107 Package (0x04) { 0x0009FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
108 Package (0x04) { 0x0009FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
110 Package (0x04) { 0x000AFFFF, 0x00, \_SB.PCI0.LEMA, 0x00 },
112 Package (0x04) { 0x000BFFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
113 Package (0x04) { 0x000BFFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
114 Package (0x04) { 0x000BFFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
115 Package (0x04) { 0x000BFFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
117 Package (0x04) { 0x000CFFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
118 Package (0x04) { 0x000CFFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
119 Package (0x04) { 0x000CFFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
120 Package (0x04) { 0x000CFFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
122 Package (0x04) { 0x000DFFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },
123 Package (0x04) { 0x000DFFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
124 Package (0x04) { 0x000DFFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
125 Package (0x04) { 0x000DFFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
127 Package (0x04) { 0x000EFFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
128 Package (0x04) { 0x000EFFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
129 Package (0x04) { 0x000EFFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
130 Package (0x04) { 0x000EFFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
135 Name (_ADR, 0x00090000)
137 Name (_PRT, Package () {
139 Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
140 Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x10 },
141 Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
142 Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
149 Name (_ADR, 0x000d0000)
156 Name (_ADR, 0x000e0000)
161 Name (_HID, EisaId ("PNP0A05"))
162 Name (_ADR, 0x00010000)
164 OperationRegion (CF44, PCI_Config, 0x44, 0x04)
165 Field (CF44, ByteAcc, NoLock, Preserve)
170 /* PS/2 keyboard (seems to be important for WinXP install) */
173 Name (_HID, EisaId ("PNP0303"))
174 Method (_STA, 0, NotSerialized)
178 Method (_CRS, 0, NotSerialized)
180 Name (TMP, ResourceTemplate () {
181 IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
182 IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
192 Name (_HID, EisaId ("PNP0F13"))
193 Method (_STA, 0, NotSerialized)
197 Method (_CRS, 0, NotSerialized)
199 Name (TMP, ResourceTemplate () {
209 Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP
210 Method (_STA, 0, NotSerialized)
214 Method (_CRS, 0, NotSerialized)
216 Name (TMP, ResourceTemplate () {
217 FixedIO (0x0378, 0x10)
224 /* Floppy controller */
227 Name (_HID, EisaId ("PNP0700"))
228 Method (_STA, 0, NotSerialized)
232 Method (_CRS, 0, NotSerialized)
234 Name (BUF0, ResourceTemplate () {
235 FixedIO (0x03F0, 0x08)
237 DMA (Compatibility, NotBusMaster, Transfer8) {2}
245 Name (_HID, EisaId ("PNP0103"))
246 Name (CRS, ResourceTemplate ()
248 Memory32Fixed (ReadOnly,
253 Method (_STA, 0, NotSerialized)
257 Method (_CRS, 0, NotSerialized)
259 CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._BAS, HPT)