2 * This file is part of the coreboot project.
4 * Copyright (C) 2009 Michael Gold <mgold@ncf.ca>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
23 #include <device/pci_def.h>
25 #include <device/pnp_def.h>
26 #include <console/console.h>
27 #include <southbridge/intel/i82801ax/i82801ax.h>
28 #include <northbridge/intel/i82810/raminit.h>
29 #include "drivers/pc80/udelay_io.c"
31 #include <cpu/x86/bist.h>
32 #include <superio/smsc/smscsuperio/smscsuperio.h>
35 #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
37 #include <cpu/intel/romstage.h>
38 void main(unsigned long bist
)
40 smscsuperio_enable_serial(SERIAL_DEV
, CONFIG_TTYS0_BASE
);
43 report_bist_failure(bist
);
46 sdram_set_registers();
47 sdram_set_spd_registers();