src/mainboard/hp/abm/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2014 Sage Electronic Engineering, LLC
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.
  19  */
  20
  21 #include <stdint.h>
  22 #include <string.h>
  23 #include <device/pci_def.h>
  24 #include <device/pci_ids.h>
  25 #include <arch/acpi.h>
  26 #include <arch/io.h>
  27 #include <arch/stages.h>
  28 #include <device/pnp_def.h>
  29 #include <arch/cpu.h>
  30 #include <cpu/x86/lapic.h>
  31 #include <console/console.h>
  32 #include <console/loglevel.h>
  33 #include <cpu/amd/car.h>
  34 #include <northbridge/amd/agesa/agesawrapper.h>
  35 #include <cpu/x86/bist.h>
  36 #include <cpu/x86/lapic.h>
  37 #include <southbridge/amd/agesa/hudson/hudson.h>
  38 #include <cpu/amd/agesa/s3_resume.h>
  39 #include <cbmem.h>
  40 #include <superio/nuvoton/common/nuvoton.h>
  41 #include <superio/nuvoton/nct5104d/nct5104d.h>
  42
  43 #define SERIAL_DEV PNP_DEV(0x4E, NCT5104D_SP4)
  44
  45 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  46 {
  47         u32 val, t32;
  48         u32 *addr32;
  49
  50
  51         amd_initmmio();
  52
  53         /* Set LPC decode enables. */
  54         pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
  55         pci_write_config32(dev, 0x44, 0xff03ffd5);
  56
  57         hudson_lpc_port80();
  58
  59         /* Enable the AcpiMmio space */
  60         outb(0x24, 0xcd6);
  61         outb(0x01, 0xcd7);
  62
  63         /* Set auxiliary output clock frequency on OSCOUT1 pin to be 25MHz */
  64         /* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */
  65         addr32 = (u32 *)0xfed80e28;
  66         t32 = *addr32;
  67         t32 &= 0xffc0ffff; // Clr bits [21:19] & [18:16]
  68         t32 |= 0x00010000; // Set bit 16 for 25MHz
  69         *addr32 = t32;
  70
  71         /* Enable Auxiliary OSCOUT1/OSCOUT2 */
  72         addr32 = (u32 *)0xfed80e40;
  73         t32 = *addr32;
  74         t32 &= 0xffffff7b; // clear 2, 7
  75         *addr32 = t32;
  76
  77         if (!cpu_init_detectedx && boot_cpu()) {
  78                 post_code(0x30);
  79                 post_code(0x31);
  80
  81                 nct5104d_enable_uartd(SERIAL_DEV);
  82                 nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  83                 console_init();
  84         }
  85
  86         /* Halt if there was a built in self test failure */
  87         post_code(0x34);
  88         report_bist_failure(bist);
  89
  90         /* Load MPB */
  91         val = cpuid_eax(1);
  92         printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
  93         printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
  94
  95         post_code(0x37);
  96         agesawrapper_amdinitreset();
  97         post_code(0x38);
  98         printk(BIOS_DEBUG, "Got past yangtze_early_setup\n");
  99
 100         post_code(0x39);
 101
 102         agesawrapper_amdinitearly();
 103         int s3resume = acpi_is_wakeup_s3();
 104         if (!s3resume) {
 105                 post_code(0x40);
 106                 agesawrapper_amdinitpost();
 107                 post_code(0x41);
 108                 agesawrapper_amdinitenv();
 109                 /* TODO: Disable cache is not ok. */
 110                 disable_cache_as_ram();
 111         } else { /* S3 detect */
 112                 printk(BIOS_INFO, "S3 detected\n");
 113
 114                 post_code(0x60);
 115                 agesawrapper_amdinitresume();
 116
 117                 amd_initcpuio();
 118                 agesawrapper_amds3laterestore();
 119
 120                 post_code(0x61);
 121                 prepare_for_resume();
 122         }
 123
 124         outb(0xEA, 0xCD6);
 125         outb(0x1, 0xcd7);
 126
 127         post_code(0x50);
 128         copy_and_run();
 129
 130         post_code(0x54);  /* Should never see this post code. */
 131 }