src/mainboard/google/rambi/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2013 Google Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc.
  18  */
  19
  20 #include <stdint.h>
  21 #include <string.h>
  22 #include <cbfs.h>
  23 #include <console/console.h>
  24 #include <soc/gpio.h>
  25 #include <soc/mrc_wrapper.h>
  26 #include <soc/romstage.h>
  27
  28 /*
  29  * RAM_ID[2:0] are on GPIO_SSUS[39:37]
  30  * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
  31  * 0b001 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
  32  * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
  33  * 0b011 - 2GiB total - 2 x 1GiB Hynix  H5TC2G63FFR-PBA 1600MHz
  34  * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
  35  * 0b101 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
  36  */
  37 static const uint32_t dual_channel_config =
  38         (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3);
  39
  40 #define SPD_SIZE 256
  41 #define GPIO_SSUS_37_PAD 57
  42 #define GPIO_SSUS_38_PAD 50
  43 #define GPIO_SSUS_39_PAD 58
  44
  45 static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual)
  46 {
  47         int ram_id = 0;
  48
  49         /* The ram_id[2:0] pullups on rambi are too large for the default 20K
  50          * pulldown on the pad. Therefore, disable the internal pull resistor to
  51          * read high values correctly. */
  52         ssus_disable_internal_pull(GPIO_SSUS_37_PAD);
  53         ssus_disable_internal_pull(GPIO_SSUS_38_PAD);
  54         ssus_disable_internal_pull(GPIO_SSUS_39_PAD);
  55
  56         ram_id |= (ssus_get_gpio(GPIO_SSUS_37_PAD) << 0);
  57         ram_id |= (ssus_get_gpio(GPIO_SSUS_38_PAD) << 1);
  58         ram_id |= (ssus_get_gpio(GPIO_SSUS_39_PAD) << 2);
  59
  60         printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds);
  61
  62         if (ram_id >= total_spds)
  63                 return NULL;
  64
  65         /* Single channel configs */
  66         if (dual_channel_config & (1 << ram_id))
  67                 *dual = 1;
  68
  69         return &spd_file_content[SPD_SIZE * ram_id];
  70 }
  71
  72 void mainboard_romstage_entry(struct romstage_params *rp)
  73 {
  74         struct cbfs_file *spd_file;
  75         void *spd_content;
  76         int dual_channel = 0;
  77
  78         struct mrc_params mp = {
  79                 .mainboard = {
  80                         .dram_type = DRAM_DDR3L,
  81                         .dram_info_location = DRAM_INFO_SPD_MEM,
  82                         .weaker_odt_settings = 1,
  83                 },
  84         };
  85
  86         spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin");
  87         if (!spd_file)
  88                 die("SPD data not found.");
  89
  90         spd_content = get_spd_pointer(CBFS_SUBHEADER(spd_file),
  91                                       ntohl(spd_file->len) / SPD_SIZE,
  92                                       &dual_channel);
  93         mp.mainboard.dram_data[0] = spd_content;
  94         if (dual_channel)
  95                 mp.mainboard.dram_data[1] = spd_content;
  96
  97         rp->mrc_params = &mp;
  98         romstage_common(rp);
  99 }