src/mainboard/google/peppy/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2010 coresystems GmbH
   5  * Copyright (C) 2012 Google Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.
  19  */
  20
  21 #include <delay.h>
  22 #include <stdint.h>
  23 #include <stdlib.h>
  24 #include <string.h>
  25 #include <cbfs.h>
  26 #include <console/console.h>
  27 #include <cpu/intel/haswell/haswell.h>
  28 #include "ec/google/chromeec/ec.h"
  29 #include <northbridge/intel/haswell/haswell.h>
  30 #include <northbridge/intel/haswell/raminit.h>
  31 #include <southbridge/intel/lynxpoint/pch.h>
  32 #include <southbridge/intel/lynxpoint/lp_gpio.h>
  33 #include "gpio.h"
  34 #include "onboard.h"
  35
  36 const struct rcba_config_instruction rcba_config[] = {
  37
  38         /*
  39          *             GFX    INTA -> PIRQA (MSI)
  40          * D28IP_P1IP  PCIE   INTA -> PIRQA
  41          * D29IP_E1P   EHCI   INTA -> PIRQD
  42          * D20IP_XHCI  XHCI   INTA -> PIRQC (MSI)
  43          * D31IP_SIP   SATA   INTA -> PIRQF (MSI)
  44          * D31IP_SMIP  SMBUS  INTB -> PIRQG
  45          * D31IP_TTIP  THRT   INTC -> PIRQA
  46          * D27IP_ZIP   HDA    INTA -> PIRQG (MSI)
  47          */
  48
  49         /* Device interrupt pin register (board specific) */
  50         RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
  51                         (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)),
  52         RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)),
  53         RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
  54                         (INTB << D28IP_P4IP)),
  55         RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)),
  56         RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)),
  57         RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)),
  58         RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)),
  59
  60         /* Device interrupt route registers */
  61         RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */
  62         RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */
  63         RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */
  64         RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */
  65         RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */
  66         RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */
  67         RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */
  68         RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */
  69
  70         /* Disable unused devices (board specific) */
  71         RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
  72
  73         RCBA_END_CONFIG,
  74 };
  75
  76 /* Copy SPD data for on-board memory */
  77 static void copy_spd(struct pei_data *peid)
  78 {
  79         const int gpio_vector[] = {13, 9, 47, -1};
  80         int spd_index = get_gpios(gpio_vector);
  81         char *spd_file;
  82         size_t spd_file_len;
  83
  84         printk(BIOS_DEBUG, "SPD index %d\n", spd_index);
  85         spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin",
  86                                          CBFS_TYPE_SPD, &spd_file_len);
  87         if (!spd_file)
  88                 die("SPD data not found.");
  89
  90         switch (google_chromeec_get_board_version()) {
  91         case PEPPY_BOARD_VERSION_PROTO:
  92                 /* Index 0 is 2GB config with CH0 only. */
  93                 if (spd_index == 0)
  94                         peid->dimm_channel1_disabled = 3;
  95                 break;
  96
  97         case PEPPY_BOARD_VERSION_EVT:
  98         default:
  99                 /* Index 0-2 are 4GB config with both CH0 and CH1.
 100                  * Index 4-6 are 2GB config with CH0 only. */
 101                 if (spd_index > 3)
 102                         peid->dimm_channel1_disabled = 3;
 103                 break;
 104         }
 105
 106         if (spd_file_len <
 107             ((spd_index + 1) * sizeof(peid->spd_data[0]))) {
 108                 printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
 109                 spd_index = 0;
 110         }
 111
 112         if (spd_file_len < sizeof(peid->spd_data[0]))
 113                 die("Missing SPD data.");
 114
 115         memcpy(peid->spd_data[0],
 116                spd_file +
 117                spd_index * sizeof(peid->spd_data[0]),
 118                sizeof(peid->spd_data[0]));
 119 }
 120
 121 void mainboard_romstage_entry(unsigned long bist)
 122 {
 123         struct pei_data pei_data = {
 124                 .pei_version = PEI_VERSION,
 125                 .mchbar = (uintptr_t)DEFAULT_MCHBAR,
 126                 .dmibar = (uintptr_t)DEFAULT_DMIBAR,
 127                 .epbar = DEFAULT_EPBAR,
 128                 .pciexbar = DEFAULT_PCIEXBAR,
 129                 .smbusbar = SMBUS_IO_BASE,
 130                 .wdbbar = 0x4000000,
 131                 .wdbsize = 0x1000,
 132                 .hpet_address = HPET_ADDR,
 133                 .rcba = (uintptr_t)DEFAULT_RCBA,
 134                 .pmbase = DEFAULT_PMBASE,
 135                 .gpiobase = DEFAULT_GPIOBASE,
 136                 .temp_mmio_base = 0xfed08000,
 137                 .system_type = 5, /* ULT */
 138                 .tseg_size = CONFIG_SMM_TSEG_SIZE,
 139                 .spd_addresses = { 0xff, 0x00, 0xff, 0x00 },
 140                 .ec_present = 1,
 141                 // 0 = leave channel enabled
 142                 // 1 = disable dimm 0 on channel
 143                 // 2 = disable dimm 1 on channel
 144                 // 3 = disable dimm 0+1 on channel
 145                 .dimm_channel0_disabled = 2,
 146                 .dimm_channel1_disabled = 2,
 147                 .max_ddr3_freq = 1600,
 148                 .usb_xhci_on_resume = 1,
 149                 .usb2_ports = {
 150                         /* Length, Enable, OCn#, Location */
 151                         { 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */
 152                           USB_PORT_MINI_PCIE },
 153                         { 0x0040, 1, 0,               /* P1: Port A, CN10 */
 154                           USB_PORT_BACK_PANEL },
 155                         { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */
 156                           USB_PORT_INTERNAL },
 157                         { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
 158                           USB_PORT_MINI_PCIE },
 159                         { 0x0040, 1, 2,               /* P4: Port B, CN6  */
 160                           USB_PORT_BACK_PANEL },
 161                         { 0x0000, 0, USB_OC_PIN_SKIP, /* P5: EMPTY */
 162                           USB_PORT_SKIP },
 163                         { 0x0150, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
 164                           USB_PORT_FLEX },
 165                         { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */
 166                           USB_PORT_SKIP },
 167                 },
 168                 .usb3_ports = {
 169                         /* Enable, OCn# */
 170                         { 1, 0               }, /* P1; Port A, CN6 */
 171                         { 0, USB_OC_PIN_SKIP }, /* P2; */
 172                         { 0, USB_OC_PIN_SKIP }, /* P3; */
 173                         { 0, USB_OC_PIN_SKIP }, /* P4; */
 174                 },
 175         };
 176
 177         struct romstage_params romstage_params = {
 178                 .pei_data = &pei_data,
 179                 .gpio_map = &mainboard_gpio_map,
 180                 .rcba_config = &rcba_config[0],
 181                 .bist = bist,
 182                 .copy_spd = copy_spd,
 183         };
 184
 185         /* Call into the real romstage main with this board's attributes. */
 186         romstage_common(&romstage_params);
 187 }