2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
21 #include <console/console.h>
22 #include <arch/smp/mpspec.h>
23 #include <arch/ioapic.h>
24 #include <device/pci.h>
28 static void *smp_write_config_table(void *v
)
30 int ioapic_id
, ioapic_ver
, isa_bus
;
31 struct mp_config_table
*mc
;
33 mc
= (void *)(((char *)v
) + SMP_FLOATING_TABLE_LEN
);
35 mptable_init(mc
, LOCAL_APIC_ADDR
);
37 smp_write_processors(mc
);
39 mptable_write_buses(mc
, NULL
, &isa_bus
);
42 ioapic_ver
= 0x11; /* External Intel 82093AA IOAPIC. */
43 smp_write_ioapic(mc
, ioapic_id
, ioapic_ver
, VIO_APIC_VADDR
);
45 /* Legacy Interrupts */
46 mptable_add_isa_interrupts(mc
, isa_bus
, ioapic_id
, 0);
48 /* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
49 smp_write_intsrc(mc
, mp_INT
, MP_IRQ_TRIGGER_LEVEL
| MP_IRQ_POLARITY_LOW
, 0x0, 0x13, ioapic_id
, 0x13);
50 smp_write_intsrc(mc
, mp_INT
, MP_IRQ_TRIGGER_LEVEL
| MP_IRQ_POLARITY_LOW
, 0x0, 0x18, ioapic_id
, 0x13);
52 /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
53 mptable_lintsrc(mc
, 0x1);
55 /* Compute the checksums. */
56 return mptable_finalize(mc
);
59 unsigned long write_smp_table(unsigned long addr
)
62 v
= smp_write_floating_table(addr
, 0);
63 return (unsigned long)smp_write_config_table(v
);