src/mainboard/asrock/e350m1/dsdt.asl

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc.
  18  */
  19
  20 /* DefinitionBlock Statement */
  21 DefinitionBlock (
  22         "DSDT.AML",     /* Output filename */
  23         "DSDT",         /* Signature */
  24         0x02,           /* DSDT Revision, needs to be 2 for 64bit */
  25         "ASROCK",       /* OEMID */
  26         "COREBOOT",     /* TABLE ID */
  27         0x00010001      /* OEM Revision */
  28         )
  29 {       /* Start of ASL file */
  30         /* #include <arch/x86/acpi/debug.asl> */        /* Include global debug methods if needed */
  31
  32         #include "acpi/mainboard.asl"
  33
  34         #include <cpu/amd/agesa/family14/acpi/cpu.asl>
  35
  36         #include "acpi/routing.asl"
  37
  38         Scope(\_SB) {
  39                 /* global utility methods expected within the \_SB scope */
  40                 #include <arch/x86/acpi/globutil.asl>
  41
  42                 Device(PCI0) {
  43
  44                         /* Describe the AMD Northbridge */
  45                         #include <northbridge/amd/agesa/family14/acpi/northbridge.asl>
  46
  47                         /* Describe the AMD Fusion Controller Hub Southbridge */
  48                         #include <southbridge/amd/cimx/sb800/acpi/fch.asl>
  49
  50                 }
  51         }   /* End Scope(_SB)  */
  52
  53         /* Contains the supported sleep states for this chipset */
  54         #include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl>
  55
  56         /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
  57         #include "acpi/sleep.asl"
  58
  59         #include "acpi/gpe.asl"
  60         #include <southbridge/amd/cimx/sb800/acpi/smbus.asl>
  61         #include "acpi/thermal.asl"
  62 }
  63 /* End of ASL file */