src/mainboard/amd/persimmon/mptable.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2014 Sage Electronic Engineering, LLC.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.
  19  */
  20
  21
  22 #include <console/console.h>
  23 #include <arch/smp/mpspec.h>
  24 #include <device/pci.h>
  25 #include <arch/io.h>
  26 #include <string.h>
  27 #include <stdint.h>
  28 #include <cpu/amd/amdfam14.h>
  29 #include <SBPLATFORM.h>
  30 #include <southbridge/amd/common/amd_pci_util.h>
  31 #include <drivers/generic/ioapic/chip.h>
  32 #include <arch/ioapic.h>
  33
  34 static void *smp_write_config_table(void *v)
  35 {
  36         struct mp_config_table *mc;
  37         int bus_isa;
  38
  39         /*
  40          * By the time this function gets called, the IOAPIC registers
  41          * have been written so they can be read to get the correct
  42          * APIC ID and Version
  43          */
  44         u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
  45         u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
  46
  47         /* Intialize the MP_Table */
  48         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  49
  50         mptable_init(mc, LOCAL_APIC_ADDR);
  51
  52         /*
  53          * Type 0: Processor Entries:
  54          * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
  55          * CPU Signature (Stepping, Model, Family),
  56          * Feature Flags
  57          */
  58         smp_write_processors(mc);
  59
  60         /*
  61          * Type 1: Bus Entries:
  62          * Bus ID, Bus Type
  63          */
  64         mptable_write_buses(mc, NULL, &bus_isa);
  65
  66         /*
  67          * Type 2: I/O APICs:
  68          * APIC ID, Version, APIC Flags:EN, Address
  69          */
  70         smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
  71
  72         /*
  73          * Type 3: I/O Interrupt Table Entries:
  74          * Int Type, Int Polarity, Int Level, Source Bus ID,
  75          * Source Bus IRQ, Dest APIC ID, Dest PIN#
  76          */
  77         mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
  78
  79         /* PCI interrupts are level triggered, and are
  80          * associated with a specific bus/device/function tuple.
  81          */
  82 #define PCI_INT(bus, dev, fn, pin) \
  83                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
  84
  85         /* APU Internal Graphic Device */
  86         PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
  87         PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
  88
  89         /* SMBUS / ACPI */
  90         PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
  91
  92         /* Southbridge HD Audio */
  93         PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
  94
  95         /* LPC */
  96         PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
  97
  98         /* USB */
  99         PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
 100         PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
 101         PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
 102         PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
 103         PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]);
 104
 105          /* IDE */
 106         PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]);
 107
 108         /* SATA */
 109         PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
 110
 111         /* on board NIC & Slot PCIE */
 112         PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);  /* Use INTE */
 113         PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]);  /* Use INTE */
 114
 115         /* PCI slots */
 116         device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
 117         if (dev && dev->enabled) {
 118                 u8 bus_pci = dev->link_list->secondary;
 119                 /* PCI_SLOT 0 */
 120                 PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]);      /* INTA -> INTE */
 121                 PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]);      /* INTB -> INTF */
 122                 PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]);      /* INTC -> INTG */
 123                 PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]);      /* INTD -> INTH */
 124         }
 125
 126         /* PCIe PortA */
 127         PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
 128         /* PCIe PortB */
 129         PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
 130         /* PCIe PortC */
 131         PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
 132         /* PCIe PortD */
 133         PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
 134
 135         /*Local Ints:    Type   Polarity        Trigger  Bus ID  IRQ    APIC ID PIN# */
 136 #define IO_LOCAL_INT(type, intr, apicid, pin) \
 137                 smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
 138
 139         IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
 140         IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
 141         /* There is no extension information... */
 142
 143         /* Compute the checksums */
 144         return mptable_finalize(mc);
 145 }
 146
 147 unsigned long write_smp_table(unsigned long addr)
 148 {
 149         void *v;
 150         v = smp_write_floating_table(addr, 0);  /* ADDR, Enable Virtual Wire */
 151         return (unsigned long)smp_write_config_table(v);
 152 }