src/mainboard/google/hatch/variants/baseboard/gpio.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright 2018 Google LLC
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <arch/acpi.h>
  17 #include <baseboard/gpio.h>
  18 #include <baseboard/variants.h>
  19 #include <commonlib/helpers.h>
  20
  21 static const struct pad_config gpio_table[] = {
  22         /* A0  : SAR0_INT_ODL */
  23         PAD_CFG_GPI_INT(GPP_A0, NONE, PLTRST, LEVEL),
  24         /* A1  : ESPI_IO0 */
  25         /* A2  : ESPI_IO1 */
  26         /* A3  : ESPI_IO2 */
  27         /* A4  : ESPI_IO3 */
  28         /* A5  : ESPI_CS# */
  29         /* A6  : SAR1_INT_ODL */
  30         PAD_CFG_GPI_INT(GPP_A6, NONE, PLTRST, LEVEL),
  31         /* A7  : PP3300_SOC_A */
  32         PAD_NC(GPP_A7, NONE),
  33         /* A8  : PEN_GARAGE_DET_L */
  34         PAD_CFG_GPI_GPIO_DRIVER_SCI(GPP_A8, NONE, DEEP, LEVEL, NONE),
  35         /* A9  : ESPI_CLK */
  36         /* A10 : FPMCU_PCH_BOOT1 */
  37         PAD_CFG_GPO(GPP_A10, 0, DEEP),
  38         /* A11 : PCH_SPI_FPMCU_CS_L */
  39         PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2),
  40         /* A12 : FPMCU_RST_ODL */
  41         PAD_CFG_GPO(GPP_A12, 1, DEEP),
  42         /* A13 : SUSWARN_L */
  43         PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
  44         /* A14 : ESPI_RST_L */
  45         /* A15 : SUSACK_L */
  46         PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
  47         /* A16 : SD_1P8_SEL => NC */
  48         PAD_NC(GPP_A16, NONE),
  49         /* A17 : EN_PP3300_SD_DX */
  50         PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
  51         /* A18 : EN_PP3300_WWAN */
  52         PAD_CFG_GPO(GPP_A18, 1, DEEP),
  53         /* A19 : WWAN_RADIO_DISABLE_1V8_ODL */
  54         PAD_CFG_GPO(GPP_A19, 1, DEEP),
  55         /* A20 : WLAN_INT_L */
  56         PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST, LEVEL, INVERT),
  57         /* A21 : TRACKPAD_INT_ODL */
  58         PAD_CFG_GPI_IRQ_WAKE(GPP_A21, NONE, DEEP, LEVEL, INVERT),
  59         /* A22 : FPMCU_PCH_BOOT0 */
  60         PAD_CFG_GPO(GPP_A22, 0, DEEP),
  61         /* A23 : FPMCU_PCH_INT_ODL */
  62         PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT),
  63
  64         /* B0  : CORE_VID0 */
  65         PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
  66         /* B1  : CORE_VID1 */
  67         PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
  68         /* B2  : GPP_B2 ==> NC */
  69         PAD_NC(GPP_B2, NONE),
  70         /* B3  : GPP_B3 ==> NC */
  71         PAD_NC(GPP_B3, NONE),
  72         /* B4  : GPP_B4 ==> NC */
  73         PAD_NC(GPP_B4, NONE),
  74         /* B5  : GPP_B5 ==> NC */
  75         PAD_NC(GPP_B5, NONE),
  76         /* B6  : SRCCLKREQ1 */
  77         PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
  78         /* B7  : GPP_B7 ==> NC */
  79         PAD_NC(GPP_B7, NONE),
  80         /* B8  : PCIE_14_WLAN_CLKREQ_ODL */
  81         PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
  82         /* B9  : GPP_B9 ==> NC */
  83         PAD_NC(GPP_B9, NONE),
  84         /* B10 : GPP_B10 ==> NC */
  85         PAD_NC(GPP_B10, NONE),
  86         /* B11 : EXT_PWR_GATE_L */
  87         PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
  88         /* B12 : SLP_S0_L */
  89         PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
  90         /* B13 : PLT_RST_L */
  91         PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
  92         /* B14 : GPP_B14_STRAP */
  93         PAD_NC(GPP_B14, NONE),
  94         /* B15 : H1_SLAVE_SPI_CS_L */
  95         PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
  96         /* B16 : H1_SLAVE_SPI_CLK */
  97         PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
  98         /* B17 : H1_SLAVE_SPI_MISO_R */
  99         PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
 100         /* B18 : H1_SLAVE_SPI_MOSI_R */
 101         PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
 102         /* B19 : Set to NF1 to match FSP setting it to NF1, i.e., GSPI1_CS0# */
 103         PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
 104         /* B20 : PCH_SPI_FPMCU_CLK_R */
 105         PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
 106         /* B21 : PCH_SPI_FPMCU_MISO */
 107         PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
 108         /* B22 : PCH_SPI_FPMCU_MOSI */
 109         PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
 110         /* B23 : GPP_B23_STRAP */
 111         PAD_NC(GPP_B23, NONE),
 112
 113         /* C0  : GPP_C0 => NC */
 114         PAD_NC(GPP_C0, NONE),
 115         /* C1  : PCIE_14_WLAN_WAKE_ODL */
 116         PAD_CFG_GPI_SCI_LOW(GPP_C1, NONE, DEEP, EDGE_SINGLE),
 117         /* C2  : GPP_C2 => NC */
 118         PAD_NC(GPP_C2, NONE),
 119         /* C3  : WLAN_OFF_L */
 120         PAD_CFG_GPO(GPP_C3, 1, DEEP),
 121         /* C4  : TOUCHSCREEN_DIS_L */
 122         PAD_CFG_GPO(GPP_C4, 1, DEEP),
 123         /* C5  : GPP_C5 => NC */
 124         PAD_NC(GPP_C5, NONE),
 125         /* C6  : PEN_PDCT_OD_L */
 126         PAD_NC(GPP_C6, NONE),
 127         /* C7  : PEN_IRQ_OD_L */
 128         PAD_NC(GPP_C7, NONE),
 129         /* C8  : UART_PCH_RX_DEBUG_TX */
 130         PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
 131         /* C9  : UART_PCH_TX_DEBUG_RX */
 132         PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
 133         /* C10 : GPP_10 ==> GPP_C10_TP */
 134         PAD_NC(GPP_C10, NONE),
 135         /* C11 : GPP_11 ==> EN_FP_RAILS */
 136         PAD_CFG_GPO(GPP_C11, 1, DEEP),
 137         /* C12 : GPP_C12 ==> NC */
 138         PAD_NC(GPP_C12, NONE),
 139         /* C13 : EC_PCH_INT_L */
 140         PAD_CFG_GPI_APIC(GPP_C13, NONE, PLTRST, LEVEL, INVERT),
 141         /* C14 : BT_DISABLE_L */
 142         PAD_CFG_GPO(GPP_C14, 1, DEEP),
 143         /* C15 : WWAN_DPR_SAR_ODL
 144          *
 145          * TODO: Driver doesn't use this pin as of now. In case driver starts
 146          * using this pin, expose this pin to driver.
 147          */
 148         PAD_CFG_GPO(GPP_C15, 1, DEEP),
 149         /* C16 : PCH_I2C_TRACKPAD_SDA */
 150         PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
 151         /* C17 : PCH_I2C_TRACKPAD_SCL */
 152         PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
 153         /* C18 : PCH_I2C_TOUCHSCREEN_SDA */
 154         PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
 155         /* C19 : PCH_I2C_TOUCHSCREEN_SCL */
 156         PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
 157         /* C20 : PCH_WP_OD */
 158         PAD_CFG_GPI(GPP_C20, NONE, DEEP),
 159         /* C21 : H1_PCH_INT_ODL */
 160         PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
 161         /* C22 : EC_IN_RW_OD */
 162         PAD_CFG_GPI(GPP_C22, NONE, DEEP),
 163         /* C23 : WLAN_PE_RST# */
 164         PAD_CFG_GPO(GPP_C23, 1, DEEP),
 165
 166         /* D0  : TP31 */
 167         PAD_NC(GPP_D0, NONE),
 168         /* D1  : TP16 */
 169         PAD_NC(GPP_D1, NONE),
 170         /* D2  : TP26 */
 171         PAD_NC(GPP_D2, NONE),
 172         /* D3  : TP27 */
 173         PAD_NC(GPP_D3, NONE),
 174         /* D4  : TP40 */
 175         PAD_NC(GPP_D4, NONE),
 176         /* D5  : WWAN_CONFIG_0 */
 177         PAD_NC(GPP_D5, NONE),
 178         /* D6  : WWAN_CONFIG_1 */
 179         PAD_NC(GPP_D6, NONE),
 180         /* D7  : WWAN_CONFIG_2 */
 181         PAD_NC(GPP_D7, NONE),
 182         /* D8  : WWAN_CONFIG_3 */
 183         PAD_NC(GPP_D8, NONE),
 184         /* D9  : GPP_D9 ==> EN_PP3300_DX_TOUCHSCREEN */
 185         PAD_CFG_GPO(GPP_D9, 0, DEEP),
 186         /* D10 : GPP_D10 ==> NC */
 187         PAD_NC(GPP_D10, NONE),
 188         /* D11 : GPP_D11 ==> NC */
 189         PAD_NC(GPP_D11, NONE),
 190         /* D12 : GPP_D12 */
 191         PAD_NC(GPP_D12, NONE),
 192         /* D13 : ISH_UART_RX */
 193         PAD_NC(GPP_D13, NONE),
 194         /* D14 : ISH_UART_TX */
 195         PAD_NC(GPP_D14, NONE),
 196         /* D15 : TOUCHSCREEN_RST_L */
 197         PAD_CFG_GPO(GPP_D15, 0, DEEP),
 198         /* D16 : USI_INT */
 199         PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, NONE),
 200         /* D17 : PCH_HP_SDW_CLK */
 201         PAD_NC(GPP_D17, NONE),
 202         /* D18 : PCH_HP_SDW_DAT */
 203         PAD_NC(GPP_D18, NONE),
 204         /* D19 : DMIC_CLK_0_SNDW4_CLK */
 205         PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
 206         /* D20 : DMIC_DATA_0_SNDW4_DATA */
 207         PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
 208         /* D21 : GPP_D21 ==> NC */
 209         PAD_NC(GPP_D21, NONE),
 210         /* D22 : GPP_D22 ==> NC */
 211         PAD_NC(GPP_D22, NONE),
 212         /* D23 : SPP_MCLK */
 213         PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
 214
 215         /* E0  : GPP_E0 ==> NC */
 216         PAD_NC(GPP_E0, NONE),
 217         /* E1  : M2_SSD_PEDET */
 218         PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
 219         /* E2  : GPP_E2 ==> NC */
 220         PAD_NC(GPP_E2, NONE),
 221         /* E3  : GPP_E3 ==> NC */
 222         PAD_NC(GPP_E3, NONE),
 223         /* E4  : M2_SSD_PE_WAKE_ODL */
 224         PAD_CFG_GPI(GPP_E4, NONE, DEEP),
 225         /* E5  : SATA_DEVSLP1 */
 226         PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
 227         /* E6  : M2_SSD_RST_L */
 228         PAD_NC(GPP_E6, NONE),
 229         /* E7  : GPP_E7 ==> NC */
 230         PAD_NC(GPP_E7, NONE),
 231         /* E8  : GPP_E8 ==> NC */
 232         PAD_NC(GPP_E8, NONE),
 233         /* E9  : GPP_E9 ==> NC */
 234         PAD_NC(GPP_E9, NONE),
 235         /* E10 : GPP_E10 ==> NC */
 236         PAD_NC(GPP_E10, NONE),
 237         /* E11 : USB_C_OC_OD USB_OC2 */
 238         PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
 239         /* E12 : USB_A_OC_OD USB_OC3 */
 240         PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
 241         /* E13 : USB_C0_DP_HPD */
 242         PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
 243         /* E14 : DDI2_HPD_ODL */
 244         PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 245         /* E15 : DDPD_HPD2 =>  NC */
 246         PAD_NC(GPP_E15, NONE),
 247         /* E16 : DDPE_HPD2 => NC */
 248         PAD_NC(GPP_E16, NONE),
 249         /* E17 : EDP_HPD */
 250         PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
 251         /* E18 : DDPB_CTRLCLK => NC */
 252         PAD_NC(GPP_E18, NONE),
 253         /* E19 : GPP_E19_STRAP */
 254         PAD_CFG_GPI(GPP_E19, NONE, DEEP),
 255         /* E20 : DDPC_CTRLCLK => NC */
 256         PAD_NC(GPP_E20, NONE),
 257         /* E21 : GPP_E21_STRAP */
 258         PAD_CFG_GPI(GPP_E21, NONE, DEEP),
 259         /* E22 : DDPD_CTRLCLK => NC */
 260         PAD_NC(GPP_E22, NONE),
 261         /* E23 : GPP_E23_STRAP */
 262         PAD_NC(GPP_E23, NONE),
 263
 264         /* F0  : GPIO_WWAN_WLAN_COEX3 */
 265         PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
 266         /* F1  : WWAN_RESET_1V8_ODL */
 267         PAD_CFG_GPO(GPP_F1, 1, DEEP),
 268         /* F2  : MEM_CH_SEL */
 269         PAD_CFG_GPI(GPP_F2, NONE, PLTRST),
 270         /* F3  : GPP_F3 ==> NC */
 271         PAD_NC(GPP_F3, NONE),
 272         /* F4  : CNV_BRI_DT */
 273         PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
 274         /* F5  : CNV_BRI_RSP */
 275         PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
 276         /* F6  : CNV_RGI_DT */
 277         PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
 278         /* F7  : CNV_RGI_RSP */
 279         PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1),
 280         /* F8  : UART_WWANTX_WLANRX_COEX1 */
 281         PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
 282         /* F9  : UART_WWANRX_WLANTX_COEX2 */
 283         PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
 284         /* F10 : GPP_F10 ==> NC */
 285         PAD_NC(GPP_F10, NONE),
 286         /* F11 : PCH_MEM_STRAP2 */
 287         PAD_CFG_GPI(GPP_F11, NONE, PLTRST),
 288         /* F12 : GPP_F12 ==> NC */
 289         PAD_NC(GPP_F12, NONE),
 290         /* F13 : GPP_F13 ==> NC */
 291         PAD_NC(GPP_F13, NONE),
 292         /* F14 : GPP_F14 ==> NC */
 293         PAD_NC(GPP_F14, NONE),
 294         /* F15 : GPP_F15 ==> NC */
 295         PAD_NC(GPP_F15, NONE),
 296         /* F16 : GPP_F16 ==> NC */
 297         PAD_NC(GPP_F16, NONE),
 298         /* F17 : GPP_F17 ==> NC */
 299         PAD_NC(GPP_F17, NONE),
 300         /* F18 : GPP_F18 ==> NC */
 301         PAD_NC(GPP_F18, NONE),
 302         /* F19 : GPP_F19 ==> NC */
 303         PAD_NC(GPP_F19, NONE),
 304         /* F20 : PCH_MEM_STRAP0 */
 305         PAD_CFG_GPI(GPP_F20, NONE, PLTRST),
 306         /* F21 : PCH_MEM_STRAP1 */
 307         PAD_CFG_GPI(GPP_F21, NONE, PLTRST),
 308         /* F22 : PCH_MEM_STRAP3 */
 309         PAD_CFG_GPI(GPP_F22, NONE, PLTRST),
 310         /* F23 : GPP_F23 ==> NC */
 311         PAD_NC(GPP_F23, NONE),
 312
 313         /* G0  : SD_CMD */
 314         PAD_CFG_NF(GPP_G0, NATIVE, DEEP, NF1),
 315         /* G1  : SD_DATA0 */
 316         PAD_CFG_NF(GPP_G1, NATIVE, DEEP, NF1),
 317         /* G2  : SD_DATA1 */
 318         PAD_CFG_NF(GPP_G2, NATIVE, DEEP, NF1),
 319         /* G3  : SD_DATA2 */
 320         PAD_CFG_NF(GPP_G3, NATIVE, DEEP, NF1),
 321         /* G4  : SD_DATA3 */
 322         PAD_CFG_NF(GPP_G4, NATIVE, DEEP, NF1),
 323         /* G5  : SD_CD# */
 324         PAD_CFG_NF(GPP_G5, NONE, PLTRST, NF1),
 325         /* G6  : SD_CLK */
 326         PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
 327         /* G7  : SD_WP => NC */
 328         PAD_NC(GPP_G7, NONE),
 329         /*
 330          * H0  : HP_INT_L
 331          */
 332         PAD_CFG_GPI_INT(GPP_H0, NONE, PLTRST, EDGE_BOTH),
 333         /* H1  : CNV_RF_RESET_L */
 334         PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3),
 335         /* H2  : CNV_CLKREQ0 */
 336         PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3),
 337         /* H3  : SPKR_PA_EN */
 338         PAD_CFG_GPO(GPP_H3, 0, DEEP),
 339         /* H4  : PCH_I2C_PEN_SDA */
 340         PAD_NC(GPP_H4, NONE),
 341         /* H5  : PCH_I2C_PEN_SCL */
 342         PAD_NC(GPP_H5, NONE),
 343         /* H6  : PCH_I2C_SAR0_MST_SDA */
 344         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 345         /* H7  : PCH_I2C_SAR0_MST_SCL */
 346         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 347         /* H8  : PCH_I2C_M2_AUDIO_SAR1_SDA */
 348         PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
 349         /* H9  : PCH_I2C_M2_AUDIO_SAR1_SCL */
 350         PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
 351         /* H10 : PCH_I2C_TRACKPAD_SDA */
 352         PAD_NC(GPP_H10, NONE),
 353         /* H11 : PCH_I2C_TRACKPAD_SCL */
 354         PAD_NC(GPP_H11, NONE),
 355         /* H12 : GPP_H12 ==> NC */
 356         PAD_NC(GPP_H12, NONE),
 357         /* H13 : GPP_H13 ==> NC */
 358         PAD_NC(GPP_H13, NONE),
 359         /* H14 : GPP_H14 ==> NC */
 360         PAD_NC(GPP_H14, NONE),
 361         /* H15 : GPP_H15 ==> NC */
 362         PAD_NC(GPP_H15, NONE),
 363         /* H16 : GPP_H16 ==> NC */
 364         PAD_NC(GPP_H16, NONE),
 365         /* H17 : TP1 */
 366         PAD_NC(GPP_H17, NONE),
 367         /* H18 : CPU_C10_GATE_L */
 368         PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
 369         /* H19 : GPP_H19 ==> NC */
 370         PAD_NC(GPP_H19, NONE),
 371         /* H20 : TP41 */
 372         PAD_NC(GPP_H20, NONE),
 373         /* H21 : XTAL_FREQ_SEL */
 374         PAD_NC(GPP_H21, NONE),
 375         /* H22 : GPP_H22 ==> NC */
 376         PAD_NC(GPP_H22, NONE),
 377         /* H23 : GPP_H23_STRAP */
 378         PAD_NC(GPP_H23, NONE),
 379
 380         /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_OD */
 381         PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
 382
 383         /* SD card detect VGPIO */
 384         PAD_CFG_GPI_GPIO_DRIVER(vSD3_CD_B, NONE, DEEP),
 385 };
 386
 387 const struct pad_config *base_gpio_table(size_t *num)
 388 {
 389         *num = ARRAY_SIZE(gpio_table);
 390         return gpio_table;
 391 }
 392
 393 /*
 394  * Default GPIO settings before entering sleep. Configure A12: FPMCU_RST_ODL
 395  * as GPO before entering sleep.
 396  */
 397 static const struct pad_config default_sleep_gpio_table[] = {
 398         PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */
 399 };
 400
 401 /*
 402  * GPIO settings before entering S5, which are same as
 403  * default_sleep_gpio_table but also,
 404  * turn off EN_PP3300_WWAN.
 405  */
 406 static const struct pad_config s5_sleep_gpio_table[] = {
 407         PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */
 408         PAD_CFG_GPO(GPP_A18, 0, DEEP), /* EN_PP3300_WWAN */
 409 };
 410
 411 const struct pad_config *__weak variant_sleep_gpio_table(
 412         u8 slp_typ, size_t *num)
 413 {
 414         if (slp_typ == ACPI_S5) {
 415                 *num = ARRAY_SIZE(s5_sleep_gpio_table);
 416                 return s5_sleep_gpio_table;
 417         }
 418         *num = ARRAY_SIZE(default_sleep_gpio_table);
 419         return default_sleep_gpio_table;
 420 }
 421
 422 /* GPIOs needed prior to ramstage. */
 423 static const struct pad_config early_gpio_table[] = {
 424         /* A12 : FPMCU_RST_ODL */
 425         PAD_CFG_GPO(GPP_A12, 0, DEEP),
 426         /* B15 : H1_SLAVE_SPI_CS_L */
 427         PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
 428         /* B16 : H1_SLAVE_SPI_CLK */
 429         PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
 430         /* B17 : H1_SLAVE_SPI_MISO_R */
 431         PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
 432         /* B18 : H1_SLAVE_SPI_MOSI_R */
 433         PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
 434         /* PCH_WP_OD */
 435         PAD_CFG_GPI(GPP_C20, NONE, DEEP),
 436         /* C21 : H1_PCH_INT_ODL */
 437         PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
 438         /* C23 : WLAN_PE_RST# */
 439         PAD_CFG_GPO(GPP_C23, 1, DEEP),
 440         /* F2  : MEM_CH_SEL */
 441         PAD_CFG_GPI(GPP_F2, NONE, PLTRST),
 442         /* F11 : PCH_MEM_STRAP2 */
 443         PAD_CFG_GPI(GPP_F11, NONE, PLTRST),
 444         /* F20 : PCH_MEM_STRAP0 */
 445         PAD_CFG_GPI(GPP_F20, NONE, PLTRST),
 446         /* F21 : PCH_MEM_STRAP1 */
 447         PAD_CFG_GPI(GPP_F21, NONE, PLTRST),
 448         /* F22 : PCH_MEM_STRAP3 */
 449         PAD_CFG_GPI(GPP_F22, NONE, PLTRST),
 450 };
 451
 452 const struct pad_config *base_early_gpio_table(size_t *num)
 453 {
 454         *num = ARRAY_SIZE(early_gpio_table);
 455         return early_gpio_table;
 456 }
 457
 458 static const struct cros_gpio cros_gpios[] = {
 459         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
 460         CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
 461 };
 462
 463 const struct cros_gpio *__weak variant_cros_gpios(size_t *num)
 464 {
 465         *num = ARRAY_SIZE(cros_gpios);
 466         return cros_gpios;
 467 }
 468
 469 /* Weak implementation of overrides */
 470 const struct pad_config *__weak override_gpio_table(size_t *num)
 471 {
 472         *num = 0;
 473         return NULL;
 474 }
 475
 476 const struct pad_config *__weak override_early_gpio_table(size_t *num)
 477 {
 478         *num = 0;
 479         return NULL;
 480 }