src/mainboard/lenovo/w541/romstage.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <stdint.h>
   4 #include <northbridge/intel/haswell/haswell.h>
   5 #include <northbridge/intel/haswell/raminit.h>
   6 #include <southbridge/intel/lynxpoint/pch.h>
   7 #include <option.h>
   8 #include <ec/lenovo/pmh7/pmh7.h>
   9 #include <device/pci_ops.h>
  10
  11 void mainboard_config_rcba(void)
  12 {
  13         RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA);
  14         RCBA16(D29IR) = DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC);
  15         RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA);
  16         RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD);
  17         RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD);
  18         RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH);
  19         RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
  20         RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
  21 }
  22
  23 void mb_late_romstage_setup(void)
  24 {
  25         u8 enable_peg = get_uint_option("enable_dual_graphics", 0);
  26
  27         bool power_en = pmh7_dgpu_power_state();
  28
  29         if (enable_peg != power_en)
  30                 pmh7_dgpu_power_enable(!power_en);
  31
  32         if (!enable_peg) {
  33                 // Hide disabled dGPU device
  34                 pci_and_config32(HOST_BRIDGE, DEVEN, ~DEVEN_D1F0EN);
  35         }
  36 }
  37
  38 void mb_get_spd_map(struct spd_info *spdi)
  39 {
  40         spdi->addresses[0] = 0x50;
  41         spdi->addresses[1] = 0x52;
  42         spdi->addresses[2] = 0x51;
  43         spdi->addresses[3] = 0x53;
  44 }
  45
  46 const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
  47         /* Length, Enable, OCn#, Location */
  48         { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
  49         { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
  50         { 0x0040, 1, 1, USB_PORT_BACK_PANEL },
  51         { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
  52         { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
  53         { 0x0040, 1, 2, USB_PORT_BACK_PANEL },
  54         { 0x0040, 1, 3, USB_PORT_BACK_PANEL },
  55         { 0x0040, 1, 3, USB_PORT_BACK_PANEL },
  56         { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
  57         { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
  58         { 0x0040, 1, 5, USB_PORT_BACK_PANEL },
  59         { 0x0040, 1, 5, USB_PORT_BACK_PANEL },
  60         { 0x0040, 1, 6, USB_PORT_BACK_PANEL },
  61         { 0x0040, 1, 6, USB_PORT_BACK_PANEL },
  62 };
  63
  64 const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
  65         { 1, 0 },
  66         { 1, 0 },
  67         { 1, USB_OC_PIN_SKIP },
  68         { 1, USB_OC_PIN_SKIP },
  69         { 1, 1 },
  70         { 1, 1 },
  71 };