src/soc/intel/skylake/Makefile.inc

   1 ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y)
   2
   3 subdirs-y += nhlt
   4 subdirs-y += romstage
   5 subdirs-y += ../../../cpu/intel/microcode
   6 subdirs-y += ../../../cpu/intel/turbo
   7 subdirs-y += ../../../cpu/x86/lapic
   8 subdirs-y += ../../../cpu/x86/mtrr
   9 subdirs-y += ../../../cpu/x86/smm
  10 subdirs-y += ../../../cpu/x86/tsc
  11
  12 bootblock-y += bootblock/bootblock.c
  13 bootblock-y += bootblock/cpu.c
  14 bootblock-y += i2c.c
  15 bootblock-y += bootblock/pch.c
  16 bootblock-y += bootblock/report_platform.c
  17 bootblock-$(CONFIG_UART_DEBUG) += bootblock/uart.c
  18 bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c
  19 bootblock-y += gpio.c
  20 bootblock-y += gspi.c
  21 bootblock-y += pch.c
  22 bootblock-y += pmutil.c
  23 bootblock-y += spi.c
  24
  25 verstage-y += gspi.c
  26 verstage-y += pch.c
  27 verstage-$(CONFIG_UART_DEBUG) += uart_debug.c
  28 verstage-y += pmutil.c
  29 verstage-y += i2c.c
  30 verstage-y += spi.c
  31
  32 romstage-y += gpio.c
  33 romstage-y += gspi.c
  34 romstage-y += i2c.c
  35 romstage-y += memmap.c
  36 romstage-y += me.c
  37 romstage-y += pch.c
  38 romstage-y += pei_data.c
  39 romstage-y += pmutil.c
  40 romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
  41 romstage-y += spi.c
  42 romstage-$(CONFIG_UART_DEBUG) += uart_debug.c
  43
  44 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
  45 ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += chip.c
  46 ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += chip_fsp20.c
  47 ramstage-y += cpu.c
  48 ramstage-y += dsp.c
  49 ramstage-y += elog.c
  50 ramstage-y += finalize.c
  51 ramstage-y += gpio.c
  52 ramstage-y += gspi.c
  53 ramstage-y += i2c.c
  54 ramstage-y += igd.c
  55 ramstage-y += irq.c
  56 ramstage-y += lockdown.c
  57 ramstage-y += lpc.c
  58 ramstage-y += me.c
  59 ramstage-y += memmap.c
  60 ramstage-y += pch.c
  61 ramstage-y += pei_data.c
  62 ramstage-y += pmc.c
  63 ramstage-y += pmutil.c
  64 ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
  65 ramstage-y += sd.c
  66 ramstage-y += smi.c
  67 ramstage-y += smmrelocate.c
  68 ramstage-y += spi.c
  69 ramstage-y += systemagent.c
  70 ramstage-y += uart.c
  71 ramstage-$(CONFIG_UART_DEBUG) += uart_debug.c
  72 ramstage-y += vr_config.c
  73
  74 smm-y += gpio.c
  75 smm-y += pch.c
  76 smm-y += pmutil.c
  77 smm-y += smihandler.c
  78 smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
  79 smm-$(CONFIG_UART_DEBUG) += uart_debug.c
  80 smm-y += uart.c
  81
  82 postcar-y += memmap.c
  83 postcar-$(CONFIG_UART_DEBUG) += uart_debug.c
  84
  85 # cpu_microcode_bins += ???
  86
  87 CPPFLAGS_common += -I$(src)/soc/intel/skylake
  88 CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
  89
  90 ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y)
  91 CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp11
  92 CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake
  93 else
  94 CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp20
  95 CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/skykabylake
  96 endif
  97
  98 # Currently used for microcode path.
  99 CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR)
 100
 101 ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi -O2
 102
 103 endif