src/mainboard/packardbell/ms2290/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
   6  * Copyright (C) 2013 Vladimir Serbinenko <phcoder@gmail.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; version 2 of
  11  * the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  21  * MA 02110-1301 USA
  22  */
  23
  24 /* __PRE_RAM__ means: use "unsigned" for device, not a struct.  */
  25
  26 #include <stdint.h>
  27 #include <string.h>
  28 #include <arch/io.h>
  29 #include <device/pci_def.h>
  30 #include <device/pnp_def.h>
  31 #include <cpu/x86/lapic.h>
  32 #include <lib.h>
  33 #include <pc80/mc146818rtc.h>
  34 #include <console/console.h>
  35 #include <cpu/x86/bist.h>
  36 #include <ec/acpi/ec.h>
  37 #include <delay.h>
  38 #include <timestamp.h>
  39 #include <cbmem.h>
  40
  41 #include "arch/early_variables.h"
  42 #include "southbridge/intel/ibexpeak/pch.h"
  43 #include "northbridge/intel/nehalem/nehalem.h"
  44
  45 #include "northbridge/intel/nehalem/raminit.h"
  46 #include "southbridge/intel/ibexpeak/me.h"
  47
  48 static void pch_enable_lpc(void)
  49 {
  50         /* Enable EC, PS/2 Keyboard/Mouse */
  51         pci_write_config16(PCH_LPC_DEV, LPC_EN,
  52                            CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
  53                            COMA_LPC_EN);
  54
  55         pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 & ~3) | 0x00040001);
  56
  57         pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
  58
  59         pci_write_config32(PCH_LPC_DEV, 0xd0, 0x0);
  60         pci_write_config32(PCH_LPC_DEV, 0xdc, 0x8);
  61
  62         pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3,
  63                           (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1);
  64
  65         pci_write_config32(PCH_LPC_DEV, ETR3,
  66                            pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR);
  67 }
  68
  69 static void rcba_config(void)
  70 {
  71         static const u32 rcba_dump3[] = {
  72                 /* 30fc */ 0x00000000,
  73                 /* 3100 */ 0x04341200, 0x00000000, 0x40043214, 0x00014321,
  74                 /* 3110 */ 0x00000002, 0x30003214, 0x00000001, 0x00000002,
  75                 /* 3120 */ 0x00000000, 0x00002321, 0x00000000, 0x00000000,
  76                 /* 3130 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  77                 /* 3140 */ 0x00003107, 0x76543210, 0x00000010, 0x00007654,
  78                 /* 3150 */ 0x00000004, 0x00000000, 0x00000000, 0x00003210,
  79                 /* 3160 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  80                 /* 3170 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  81                 /* 3180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  82                 /* 3190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  83                 /* 31a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  84                 /* 31b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  85                 /* 31c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  86                 /* 31d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  87                 /* 31e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  88                 /* 31f0 */ 0x00000000, 0x00000000, 0x00000000, 0x03000000,
  89                 /* 3200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  90                 /* 3210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  91                 /* 3220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  92                 /* 3230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  93                 /* 3240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  94                 /* 3250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  95                 /* 3260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  96                 /* 3270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  97                 /* 3280 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  98                 /* 3290 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  99                 /* 32a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 100                 /* 32b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 101                 /* 32c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 102                 /* 32d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 103                 /* 32e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 104                 /* 32f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 105                 /* 3300 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 106                 /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000,
 107                 /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000,
 108                 /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 109                 /* 3340 */ 0x000fffff, 0x00000000, 0x00000000, 0x00000000,
 110                 /* 3350 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 111                 /* 3360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 112                 /* 3370 */ 0x00000000, 0x00000000, 0x7f8fdfff, 0x00000000,
 113                 /* 3380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 114                 /* 3390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 115                 /* 33a0 */ 0x00003900, 0x00000000, 0x00000000, 0x00000000,
 116                 /* 33b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 117                 /* 33c0 */ 0x00010000, 0x00000000, 0x00000000, 0x0001004b,
 118                 /* 33d0 */ 0x06000008, 0x00010000, 0x00000000, 0x00000000,
 119                 /* 33e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 120                 /* 33f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 121                 /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000,
 122                 /* 3410 */ 0x00000c61, 0x00000000, 0x16fc1fe1, 0xbf4f001f,
 123                 /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000,
 124                 /* 3430 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 125                 /* 3440 */ 0xdeaddeed, 0x00000000, 0x00000000, 0x00000000,
 126                 /* 3450 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 127                 /* 3460 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 128                 /* 3470 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 129                 /* 3480 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 130                 /* 3490 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 131                 /* 34a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 132                 /* 34b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 133                 /* 34c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 134                 /* 34d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 135                 /* 34e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 136                 /* 34f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 137                 /* 3500 */ 0x20000557, 0x2000055f, 0x2000074b, 0x2000074b,
 138                 /* 3510 */ 0x20000557, 0x2000014b, 0x2000074b, 0x2000074b,
 139                 /* 3520 */ 0x2000074b, 0x2000074b, 0x2000055f, 0x2000055f,
 140                 /* 3530 */ 0x20000557, 0x2000055f, 0x00000000, 0x00000000,
 141                 /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 142                 /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 143                 /* 3560 */ 0x00000001, 0x000026a3, 0x00040002, 0x01000052,
 144                 /* 3570 */ 0x02000772, 0x16000f8f, 0x1800ff4f, 0x0001d630,
 145                 /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 146                 /* 3590 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 147                 /* 35a0 */ 0xfc000201, 0x3c000201, 0x00000000, 0x00000000,
 148                 /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 149                 /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 150                 /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 151                 /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 152                 /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 153                 /* 3600 */ 0x0a001f00, 0x00000000, 0x00000000, 0x00000001,
 154                 /* 3610 */ 0x00010000, 0x00000000, 0x00000000, 0x00000000,
 155                 /* 3600 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 156                 /* 3610 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 157                 /* 3620 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 158                 /* 3630 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 159                 /* 3640 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 160                 /* 3650 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 161                 /* 3660 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 162                 /* 3670 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 163                 /* 3680 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 164                 /* 3690 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 165                 /* 36a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 166                 /* 36b0 */ 0x00000000, 0x089c0018, 0x00000000, 0x00000000,
 167                 /* 36c0 */ 0x11111111, 0x00000000, 0x00000000, 0x00000000,
 168                 /* 36d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 169                 /* 36e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 170                 /* 36f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 171                 /* 3710 */ 0x00000000, 0x4e564d49, 0x00000000, 0x00000000,
 172         };
 173         unsigned i;
 174         for (i = 0; i < sizeof(rcba_dump3) / 4; i++) {
 175                 RCBA32(4 * i + 0x30fc) = rcba_dump3[i];
 176                 (void)RCBA32(4 * i + 0x30fc);
 177         }
 178 }
 179
 180 static inline void write_acpi32(u32 addr, u32 val)
 181 {
 182         outl(val, DEFAULT_PMBASE | addr);
 183 }
 184
 185 static inline void write_acpi16(u32 addr, u16 val)
 186 {
 187         outw(val, DEFAULT_PMBASE | addr);
 188 }
 189
 190 static inline u32 read_acpi32(u32 addr)
 191 {
 192         return inl(DEFAULT_PMBASE | addr);
 193 }
 194
 195 static inline u16 read_acpi16(u32 addr)
 196 {
 197         return inw(DEFAULT_PMBASE | addr);
 198 }
 199
 200 void main(unsigned long bist)
 201 {
 202         u32 reg32;
 203         int s3resume = 0;
 204         const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
 205
 206         timestamp_init(rdtsc ());
 207
 208         /* SERR pin is confused on reset. Clear NMI.  */
 209         outb(4, 0x61);
 210         outb(0, 0x61);
 211
 212         timestamp_add_now(TS_START_ROMSTAGE);
 213
 214         if (bist == 0)
 215                 enable_lapic();
 216
 217         nehalem_early_initialization(NEHALEM_MOBILE);
 218
 219         pch_enable_lpc();
 220
 221         /* Enable GPIOs */
 222         pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
 223         pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
 224         outl (0x796bd9c3, DEFAULT_GPIOBASE);
 225         outl (0x86fec7c2, DEFAULT_GPIOBASE + 4);
 226         outl (0xe4e8d7fe, DEFAULT_GPIOBASE + 0xc);
 227         outl (0, DEFAULT_GPIOBASE + 0x18);
 228         outl (0x00004182, DEFAULT_GPIOBASE + 0x2c);
 229         outl (0x123360f8, DEFAULT_GPIOBASE + 0x30);
 230         outl (0x1f47bfa8, DEFAULT_GPIOBASE + 0x34);
 231         outl (0xfffe7fb6, DEFAULT_GPIOBASE + 0x38);
 232
 233
 234         /* This should probably go away. Until now it is required
 235          * and mainboard specific
 236          */
 237         rcba_config();
 238
 239         console_init();
 240
 241         /* Halt if there was a built in self test failure */
 242         report_bist_failure(bist);
 243
 244         /* Read PM1_CNT */
 245         reg32 = inl(DEFAULT_PMBASE + 0x04);
 246         printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
 247         if (((reg32 >> 10) & 7) == 5) {
 248                 u8 reg8;
 249                 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
 250                 printk(BIOS_DEBUG, "a2: %02x\n", reg8);
 251                 if (!(reg8 & 0x20)) {
 252                         outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
 253                         printk(BIOS_DEBUG, "Bad resume from S3 detected.\n");
 254                 } else {
 255                         printk(BIOS_DEBUG, "Resume from S3 detected.\n");
 256                         s3resume = 1;
 257                 }
 258         }
 259
 260         /* Enable SMBUS. */
 261         enable_smbus();
 262
 263         write_acpi16(0x2, 0x0);
 264         write_acpi32(0x28, 0x0);
 265         write_acpi32(0x2c, 0x0);
 266         if (!s3resume) {
 267                 read_acpi32(0x4);
 268                 read_acpi32(0x20);
 269                 read_acpi32(0x34);
 270                 write_acpi16(0x0, 0x900);
 271                 write_acpi32(0x20, 0xffff7ffe);
 272                 write_acpi32(0x34, 0x56974);
 273                 pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3,
 274                                   pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) | 2);
 275         }
 276
 277         early_thermal_init();
 278
 279         timestamp_add_now(TS_BEFORE_INITRAM);
 280
 281         chipset_init(s3resume);
 282         raminit(s3resume, spd_addrmap);
 283
 284         timestamp_add_now(TS_AFTER_INITRAM);
 285
 286         intel_early_me_status();
 287
 288         if (s3resume) {
 289                 /* Clear SLP_TYPE. This will break stage2 but
 290                  * we care for that when we get there.
 291                  */
 292                 reg32 = inl(DEFAULT_PMBASE + 0x04);
 293                 outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
 294         }
 295
 296 #if CONFIG_HAVE_ACPI_RESUME
 297         /* If there is no high memory area, we didn't boot before, so
 298          * this is not a resume. In that case we just create the cbmem toc.
 299          */
 300         if (s3resume) {
 301                 void *resume_backup_memory;
 302
 303                 /* For non-S3-resume, CBMEM is inited in raminit code.  */
 304                 if (cbmem_recovery(1)) {
 305                         printk(BIOS_ERR, "Failed S3 resume.\n");
 306                         ram_check(0x100000, 0x200000);
 307
 308                         /* Failed S3 resume, reset to come up cleanly */
 309                         outb(0xe, 0xcf9);
 310                         hlt();
 311                 }
 312
 313                 resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
 314
 315                 /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
 316                  * through stage 2. We could keep stuff like stack and heap in high tables
 317                  * memory completely, but that's a wonderful clean up task for another
 318                  * day.
 319                  */
 320                 if (resume_backup_memory)
 321                         memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE,
 322                                HIGH_MEMORY_SAVE);
 323
 324                 /* Magic for S3 resume */
 325                 pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
 326         } else {
 327                 pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
 328                 quick_ram_check();
 329         }
 330 #endif
 331
 332         timestamp_add_now(TS_END_ROMSTAGE);
 333 }