src/mainboard/packardbell/ms2290/mainboard.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
   6  * Copyright (C) 2013 Vladimir Serbinenko <phcoder@gmail.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; version 2 of
  11  * the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  21  * MA 02110-1301 USA
  22  */
  23
  24 #include <console/console.h>
  25 #include <device/device.h>
  26 #include <arch/io.h>
  27 #include <delay.h>
  28 #include <device/pci_def.h>
  29 #include <device/pci_ops.h>
  30 #include <device/pci_ids.h>
  31 #include <arch/io.h>
  32 #include <northbridge/intel/nehalem/nehalem.h>
  33 #include <southbridge/intel/bd82x6x/pch.h>
  34 #include <ec/acpi/ec.h>
  35
  36 #include <pc80/mc146818rtc.h>
  37 #include "hda_verb.h"
  38 #include <arch/x86/include/arch/acpigen.h>
  39 #if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
  40 #include <x86emu/regs.h>
  41 #include <arch/interrupt.h>
  42 #endif
  43 #include <pc80/keyboard.h>
  44 #include <cpu/x86/lapic.h>
  45 #include <device/pci.h>
  46 #include <smbios.h>
  47
  48 static acpi_cstate_t cst_entries[] = {
  49         {1, 1, 1000, {0x7f, 1, 2, {0}, 1, 0}},
  50         {2, 1, 500, {0x01, 8, 0, {0}, DEFAULT_PMBASE + LV2, 0}},
  51         {2, 17, 250, {0x01, 8, 0, {0}, DEFAULT_PMBASE + LV3, 0}},
  52 };
  53
  54 int get_cst_entries(acpi_cstate_t ** entries)
  55 {
  56         *entries = cst_entries;
  57         return ARRAY_SIZE(cst_entries);
  58 }
  59
  60 #if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
  61
  62 static int int15_handler(void)
  63 {
  64         switch ((X86_EAX & 0xffff)) {
  65                 /* Get boot display.  */
  66         case 0x5f35:
  67                 X86_EAX = 0x5f;
  68                 /* The flags are:
  69                    1 - VGA
  70                    4 - DisplayPort
  71                    8 - LCD
  72                  */
  73                 X86_ECX = 0x8;
  74
  75                 return 1;
  76         case 0x5f40:
  77                 X86_EAX = 0x5f;
  78                 X86_ECX = 0x2;
  79                 return 1;
  80         default:
  81                 printk(BIOS_WARNING, "Unknown INT15 function %04x!\n",
  82                        X86_EAX & 0xffff);
  83                 return 0;
  84         }
  85 }
  86 #endif
  87
  88 /* Audio Setup */
  89
  90 extern const u32 *cim_verb_data;
  91 extern u32 cim_verb_data_size;
  92
  93 static void verb_setup(void)
  94 {
  95         cim_verb_data = mainboard_cim_verb_data;
  96         cim_verb_data_size = sizeof(mainboard_cim_verb_data);
  97 }
  98
  99 static void mainboard_enable(device_t dev)
 100 {
 101         u16 pmbase;
 102
 103         printk(BIOS_SPEW, "starting SPI configuration\n");
 104
 105         /* Configure SPI.  */
 106         RCBA32(0x3800) = 0x07ff0500;
 107         RCBA32(0x3804) = 0x3f046008;
 108         RCBA32(0x3808) = 0x0058efc0;
 109         RCBA32(0x384c) = 0x92000000;
 110         RCBA32(0x3850) = 0x00000a0b;
 111         RCBA32(0x3858) = 0x07ff0500;
 112         RCBA32(0x385c) = 0x04ff0003;
 113         RCBA32(0x3860) = 0x00020001;
 114         RCBA32(0x3864) = 0x00000fff;
 115         RCBA32(0x3874) = 0;
 116         RCBA32(0x3890) = 0xf8400000;
 117         RCBA32(0x3894) = 0x143b5006;
 118         RCBA32(0x3898) = 0x05200302;
 119         RCBA32(0x389c) = 0x0601209f;
 120         RCBA32(0x38b0) = 0x00000004;
 121         RCBA32(0x38b4) = 0x03040002;
 122         RCBA32(0x38c0) = 0x00000007;
 123         RCBA32(0x38c8) = 0x00002005;
 124         RCBA32(0x38c4) = 0x00802005;
 125         RCBA32(0x3804) = 0x3f04e008;
 126
 127         printk(BIOS_SPEW, "SPI configured\n");
 128
 129         int i;
 130         const u8 dmp[256] = {
 131                 0x00, 0x20, 0x00, 0x00, 0x00, 0x02, 0x89, 0xe4, 0x30, 0x00, 0x40, 0x14, 0x00, 0x00, 0x00, 0x11,
 132                 0x03, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 133                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 134                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 135                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0xf4, 0x01, 0x00, 0x00, 0x01,
 136                 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 137                 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 138                 0x62, 0x01, 0x04, 0x00, 0x08, 0x73, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
 139                 0x42, 0x07, 0x09, 0x09, 0xf0, 0x00, 0x00, 0xf0, 0xa9, 0x00, 0x00, 0x06, 0x00, 0x00, 0xff, 0x00,
 140                 0x00, 0x01, 0x00, 0x04, 0xff, 0xff, 0x00, 0x00, 0x00, 0xb1, 0x00, 0x00, 0x00, 0x00, 0x04, 0x0b,
 141                 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x28, 0x1b, 0x21, 0x00, 0x2c, 0x3b, 0x13, 0x00,
 142                 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
 143                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 144                 0x55, 0x5a, 0x57, 0x5c, 0x00, 0x00, 0x00, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, 0x00, 0x00,
 145                 0x52, 0x10, 0x52, 0x10, 0x64, 0x00, 0x00, 0x00, 0x74, 0x30, 0x00, 0x60, 0x00, 0x00, 0xaf, 0x0b,
 146                 0x30, 0x45, 0x2e, 0x30, 0x38, 0x41, 0x43, 0x2e, 0x30, 0x31, 0x2e, 0x31, 0x36, 0x20, 0x00, 0x00,
 147         };
 148
 149         for (i = 0; i < 256; i++)
 150                 ec_write (i, dmp[i]);
 151
 152         pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
 153                                    PMBASE) & 0xff80;
 154
 155         printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
 156
 157         outl(0, pmbase + SMI_EN);
 158
 159         enable_lapic();
 160         pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE,
 161                            DEFAULT_GPIOBASE | 1);
 162         pci_write_config8(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_CNTL,
 163                           0x10);
 164
 165 #if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
 166         /* Install custom int15 handler for VGA OPROM */
 167         mainboard_interrupt_handlers(0x15, &int15_handler);
 168 #endif
 169
 170         /* This sneaked in here, because EasyNote has no SuperIO chip.
 171          */
 172         pc_keyboard_init(0);
 173         verb_setup();
 174 }
 175
 176 struct chip_operations mainboard_ops = {
 177         .enable_dev = mainboard_enable,
 178 };