mainboard: New port Packard Bell LM85.
[coreboot.git] / src / mainboard / packardbell / ms2290 / dsdt.asl
blobd9b84e0d5d4dada2800e3847305dbd378b0ab740
1 /*
2  * This file is part of the coreboot project.
3  *
4  * Copyright (C) 2007-2009 coresystems GmbH
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation; version 2 of
9  * the License.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
19  * MA 02110-1301 USA
20  */
22 DefinitionBlock(
23         "dsdt.aml",
24         "DSDT",
25         0x03,           /* DSDT revision: ACPI v3.0 */
26         "COREv4",       /* OEM id */
27         "COREBOOT",     /* OEM table id */
28         0x20140108      /* OEM revision */
31         /* Some generic macros */
32         #include "acpi/platform.asl"
34         /* global NVS and variables */
35         #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
37         /* General Purpose Events */
38         #include "acpi/gpe.asl"
40         #include <cpu/intel/model_206ax/acpi/cpu.asl>
42         Scope (\_SB) {
43                 Device (PCI0)
44                 {
45                         #include <northbridge/intel/nehalem/acpi/nehalem.asl>
46                         #include <southbridge/intel/bd82x6x/acpi/pch.asl>
47                 }
48                 Device (UNCR)
49                 {
50                         Name (_BBN, 0xFF)
51                         Name (_ADR, 0x00)
52                         Name (RID, 0x00)
53                         Name (_HID, EisaId ("PNP0A03"))
54                         Name (_CRS, ResourceTemplate ()
55                                 {
56                                 WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
57                                                 0x0000,      /* Granularity */
58                                                 0x00FF,      /* Range Minimum */
59                                                 0x00FF,      /* Range Maximum */
60                                                 0x0000,      /* Translation Offset */
61                                                 0x0001,      /* Length */
62                                                 ,, )
63                                 })
64                         Device (SAD)
65                         {
66                                 Name (_ADR, 0x01)
67                                 Name (RID, 0x00)
68                                 OperationRegion (SADC, PCI_Config, 0x00, 0x0100)
69                                 Field (SADC, DWordAcc, NoLock, Preserve)
70                                 {
71                                         Offset (0x40),
72                                         PAM0,   8,
73                                         PAM1,   8,
74                                         PAM2,   8,
75                                         PAM3,   8,
76                                         PAM4,   8,
77                                         PAM5,   8,
78                                         PAM6,   8
79                                 }
80                         }
81                 }
82         }
84         #include "acpi/video.asl"
86         /* Chipset specific sleep states */
87         #include <southbridge/intel/i82801gx/acpi/sleepstates.asl>