src/cpu/amd/agesa/family14/model_14_init.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <console/console.h>
  21 #include <cpu/x86/msr.h>
  22 #include <cpu/amd/mtrr.h>
  23 #include <device/device.h>
  24 #include <device/pci.h>
  25 #include <string.h>
  26 #include <cpu/x86/msr.h>
  27 #include <cpu/x86/pae.h>
  28 #include <pc80/mc146818rtc.h>
  29 #include <cpu/x86/lapic.h>
  30
  31 #include <cpu/cpu.h>
  32 #include <cpu/x86/cache.h>
  33 #include <cpu/x86/mtrr.h>
  34 #include <cpu/amd/amdfam14.h>
  35
  36 #define MCI_STATUS 0x401
  37
  38 msr_t rdmsr_amd(u32 index)
  39 {
  40         msr_t result;
  41         __asm__ __volatile__(
  42                 "rdmsr"
  43                 :"=a"(result.lo), "=d"(result.hi)
  44                 :"c"(index), "D"(0x9c5a203a)
  45                 );
  46         return result;
  47 }
  48
  49 void wrmsr_amd(u32 index, msr_t msr)
  50 {
  51         __asm__ __volatile__(
  52                 "wrmsr"
  53                 : /* No outputs */
  54                 :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a)
  55                 );
  56 }
  57
  58 static void model_14_init(device_t dev)
  59 {
  60   printk(BIOS_DEBUG, "Model 14 Init.\n");
  61
  62   u8 i;
  63   msr_t msr;
  64   int msrno;
  65 #if CONFIG_LOGICAL_CPUS == 1
  66   u32 siblings;
  67 #endif
  68
  69   disable_cache ();
  70   /* Enable access to AMD RdDram and WrDram extension bits */
  71   msr = rdmsr(SYSCFG_MSR);
  72   msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
  73   wrmsr(SYSCFG_MSR, msr);
  74
  75    // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
  76    msr.lo = msr.hi = 0;
  77    wrmsr (0x259, msr);
  78    msr.lo = msr.hi = 0x1e1e1e1e;
  79    for (msrno = 0x268; msrno <= 0x26f; msrno++)
  80       wrmsr (msrno, msr);
  81
  82   /* disable access to AMD RdDram and WrDram extension bits */
  83   msr = rdmsr(SYSCFG_MSR);
  84   msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
  85   wrmsr(SYSCFG_MSR, msr);
  86   enable_cache ();
  87
  88   /* zero the machine check error status registers */
  89   msr.lo = 0;
  90   msr.hi = 0;
  91   for (i = 0; i < 6; i++) {
  92     wrmsr(MCI_STATUS + (i * 4), msr);
  93   }
  94
  95   /* Enable the local cpu apics */
  96   setup_lapic();
  97
  98 #if CONFIG_LOGICAL_CPUS == 1
  99   siblings = cpuid_ecx(0x80000008) & 0xff;
 100
 101   if (siblings > 0) {
 102     msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
 103     msr.lo |= 1 << 28;
 104     wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
 105
 106     msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
 107     msr.hi |= 1 << (33 - 32);
 108     wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
 109   }
 110   printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
 111 #endif
 112
 113   /* DisableCf8ExtCfg */
 114   msr = rdmsr(NB_CFG_MSR);
 115   msr.hi &= ~(1 << (46 - 32));
 116   wrmsr(NB_CFG_MSR, msr);
 117
 118
 119   /* Write protect SMM space with SMMLOCK. */
 120   msr = rdmsr(HWCR_MSR);
 121   msr.lo |= (1 << 0);
 122   wrmsr(HWCR_MSR, msr);
 123 }
 124
 125 static struct device_operations cpu_dev_ops = {
 126         .init = model_14_init,
 127 };
 128
 129 static struct cpu_device_id cpu_table[] = {
 130         { X86_VENDOR_AMD, 0x500f00 },   /* ON-A0 */
 131         { X86_VENDOR_AMD, 0x500f01 },   /* ON-A1 */
 132         { X86_VENDOR_AMD, 0x500f10 },   /* ON-B0 */
 133         { X86_VENDOR_AMD, 0x500f20 },   /* ON-C0 */
 134         { 0, 0 },
 135 };
 136
 137 static const struct cpu_driver model_14 __cpu_driver = {
 138         .ops      = &cpu_dev_ops,
 139         .id_table = cpu_table,
 140 };