2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
5 ## Copyright (C) 2009-2010 coresystems GmbH
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; version 2 of the License.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
17 mainmenu "coreboot configuration"
26 string "Local version string"
28 Append an extra string to the end of the coreboot version.
30 This can be useful if, for instance, you want to append the
31 respective board's hostname or some other identifying string to
32 the coreboot version number, so that you can easily distinguish
33 boot logs of different boards from each other.
36 string "CBFS prefix to use"
39 Select the prefix to all files put into the image. It's "fallback"
40 by default, "normal" is a common alternative.
43 prompt "Compiler to use"
46 This option allows you to select the compiler used for building
48 You must build the coreboot crosscompiler for the board that you
51 To build all the GCC crosscompilers (takes a LONG time), run:
54 For help on individual architectures, run the command:
60 Use the GNU Compiler Collection (GCC) to build coreboot.
62 For details see http://gcc.gnu.org.
64 config COMPILER_LLVM_CLANG
65 bool "LLVM/clang (TESTING ONLY - Not currently working)"
67 Use LLVM/clang to build coreboot. To use this, you must build the
68 coreboot version of the clang compiler. Run the command
70 Note that this option is not currently working correctly and should
71 really only be selected if you're trying to work on getting clang
74 For details see http://clang.llvm.org.
79 bool "Allow building with any toolchain"
82 Many toolchains break when building coreboot since it uses quite
83 unusual linker features. Unless developers explicitely request it,
84 we'll have to assume that they use their distro compiler by mistake.
85 Make sure that using patched compilers is a conscious decision.
88 bool "Use ccache to speed up (re)compilation"
91 Enables the use of ccache for faster builds.
93 Requires the ccache utility in your system $PATH.
95 For details see https://ccache.samba.org.
98 bool "Generate flashmap descriptor parser using flex and bison"
101 Enable this option if you are working on the flashmap descriptor
102 parser and made changes to fmd_scanner.l or fmd_parser.y.
104 Otherwise, say N to use the provided pregenerated scanner/parser.
106 config UTIL_GENPARSER
107 bool "Generate SCONFIG & BINCFG parser using flex and bison"
110 Enable this option if you are working on the sconfig device tree
111 parser or bincfg and made changes to the .l or .y files.
113 Otherwise, say N to use the provided pregenerated scanner/parser.
115 config USE_OPTION_TABLE
116 bool "Use CMOS for configuration values"
117 depends on HAVE_OPTION_TABLE
119 Enable this option if coreboot shall read options from the "CMOS"
120 NVRAM instead of using hard-coded values.
122 config STATIC_OPTION_TABLE
123 bool "Load default configuration values into CMOS on each boot"
124 depends on USE_OPTION_TABLE
126 Enable this option to reset "CMOS" NVRAM values to default on
127 every boot. Use this if you want the NVRAM configuration to
128 never be modified from its default values.
130 config COMPRESS_RAMSTAGE
131 bool "Compress ramstage with LZMA"
132 # Default value set at the end of the file
134 Compress ramstage to save memory in the flash image. Note
135 that decompression might slow down booting if the boot flash
136 is connected through a slow link (i.e. SPI).
138 config COMPRESS_PRERAM_STAGES
139 bool "Compress romstage and verstage with LZ4"
141 # Default value set at the end of the file
143 Compress romstage and (if it exists) verstage with LZ4 to save flash
144 space and speed up boot, since the time for reading the image from SPI
145 (and in the vboot case verifying it) is usually much greater than the
146 time spent decompressing. Doesn't work for XIP stages (assume all
147 ARCH_X86 for now) for obvious reasons.
149 config COMPRESS_BOOTBLOCK
152 This option can be used to compress the bootblock with LZ4 and attach
153 a small self-decompression stub to its front. This can drastically
154 reduce boot time on platforms where the bootblock is loaded over a
155 very slow connection and bootblock size trumps all other factors for
156 speed. Since this using this option usually requires changes to the
157 SoC memlayout and possibly extra support code, it should not be
158 user-selectable. (There's no real point in offering this to the user
159 anyway... if it works and saves boot time, you would always want it.)
161 config INCLUDE_CONFIG_FILE
162 bool "Include the coreboot .config file into the ROM image"
163 # Default value set at the end of the file
165 Include the .config file that was used to compile coreboot
166 in the (CBFS) ROM image. This is useful if you want to know which
167 options were used to build a specific coreboot.rom image.
169 Saying Y here will increase the image size by 2-3KB.
171 You can use the following command to easily list the options:
173 grep -a CONFIG_ coreboot.rom
175 Alternatively, you can also use cbfstool to print the image
176 contents (including the raw 'config' item we're looking for).
180 $ cbfstool coreboot.rom print
181 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
185 Name Offset Type Size
186 cmos_layout.bin 0x0 cmos layout 1159
187 fallback/romstage 0x4c0 stage 339756
188 fallback/ramstage 0x53440 stage 186664
189 fallback/payload 0x80dc0 payload 51526
190 config 0x8d740 raw 3324
191 (empty) 0x8e480 null 3610440
193 config COLLECT_TIMESTAMPS
194 bool "Create a table of timestamps collected during boot"
195 default y if ARCH_X86
197 Make coreboot create a table of timer-ID/timer-value pairs to
198 allow measuring time spent at different phases of the boot process.
200 config TIMESTAMPS_ON_CONSOLE
201 bool "Print the timestamp values on the console"
203 depends on COLLECT_TIMESTAMPS
205 Print the timestamps to the debug console if enabled at level spew.
208 bool "Allow use of binary-only repository"
210 This draws in the blobs repository, which contains binary files that
211 might be required for some chipsets or boards.
212 This flag ensures that a "Free" option remains available for users.
215 bool "Code coverage support"
216 depends on COMPILER_GCC
218 Add code coverage support for coreboot. This will store code
219 coverage information in CBMEM for extraction from user space.
223 bool "Undefined behavior sanitizer support"
226 Instrument the code with checks for undefined behavior. If unsure,
227 say N because it adds a small performance penalty and may abort
228 on code that happens to work in spite of the UB.
230 config NO_RELOCATABLE_RAMSTAGE
232 default n if ARCH_X86
235 config RELOCATABLE_RAMSTAGE
237 depends on EARLY_CBMEM_INIT
238 default !NO_RELOCATABLE_RAMSTAGE
239 select RELOCATABLE_MODULES
241 The reloctable ramstage support allows for the ramstage to be built
242 as a relocatable module. The stage loader can identify a place
243 out of the OS way so that copying memory is unnecessary during an S3
244 wake. When selecting this option the romstage is responsible for
245 determing a stack location to use for loading the ramstage.
247 config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
248 depends on RELOCATABLE_RAMSTAGE
251 The relocated ramstage is saved in an area specified by the
252 by the board and/or chipset.
255 bool "Update existing coreboot.rom image"
257 If this option is enabled, no new coreboot.rom file
258 is created. Instead it is expected that there already
259 is a suitable file for further processing.
260 The bootblock will not be modified.
262 If unsure, select 'N'
264 config BOOTSPLASH_IMAGE
265 bool "Add a bootsplash image"
267 Select this option if you have a bootsplash image that you would
268 like to add to your ROM.
270 This will only add the image to the ROM. To actually run it check
271 options under 'Display' section.
273 config BOOTSPLASH_FILE
274 string "Bootsplash path and filename"
275 depends on BOOTSPLASH_IMAGE
276 # Default value set at the end of the file
278 The path and filename of the file to use as graphical bootsplash
279 screen. The file format has to be jpg.
285 source "src/mainboard/Kconfig"
289 default "devicetree.cb"
291 This symbol allows mainboards to select a different file under their
292 mainboard directory for the devicetree.cb file. This allows the board
293 variants that need different devicetrees to be in the same directory.
295 Examples: "devicetree.variant.cb"
296 "variant/devicetree.cb"
298 config OVERRIDE_DEVICETREE
302 This symbol allows variants to provide an override devicetree file to
303 override the registers and/or add new devices on top of the ones
304 provided by baseboard devicetree using CONFIG_DEVICETREE.
306 Examples: "devicetree.variant-override.cb"
307 "variant/devicetree-override.cb"
310 hex "Size of CBFS filesystem in ROM"
311 # Default value set at the end of the file
313 This is the part of the ROM actually managed by CBFS, located at the
314 end of the ROM (passed through cbfstool -o) on x86 and at at the start
315 of the ROM (passed through cbfstool -s) everywhere else. It defaults
316 to span the whole ROM on all but Intel systems that use an Intel Firmware
317 Descriptor. It can be overridden to make coreboot live alongside other
318 components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
322 string "fmap description file in fmd format"
323 default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
326 The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
327 but in some cases more complex setups are required.
328 When an fmd is specified, it overrides the default format.
332 # load site-local kconfig to allow user specific defaults and overrides
333 source "site-local/Kconfig"
335 config SYSTEM_TYPE_LAPTOP
339 config CBFS_AUTOGEN_ATTRIBUTES
343 If this option is selected, every file in cbfs which has a constraint
344 regarding position or alignment will get an additional file attribute
345 which describes this constraint.
350 source "src/soc/*/Kconfig"
352 source "src/cpu/Kconfig"
353 comment "Northbridge"
354 source "src/northbridge/*/*/Kconfig"
355 comment "Southbridge"
356 source "src/southbridge/*/*/Kconfig"
358 source "src/superio/*/*/Kconfig"
359 comment "Embedded Controllers"
360 source "src/ec/acpi/Kconfig"
361 source "src/ec/*/*/Kconfig"
362 # FIXME move to vendorcode
363 source "src/drivers/intel/fsp1_0/Kconfig"
365 source "src/southbridge/intel/common/firmware/Kconfig"
366 source "src/vendorcode/*/Kconfig"
368 source "src/arch/*/Kconfig"
372 source "src/device/Kconfig"
374 menu "Generic Drivers"
375 source "src/drivers/*/Kconfig"
376 source "src/drivers/*/*/Kconfig"
377 source "src/commonlib/storage/Kconfig"
382 source "src/security/Kconfig"
386 source "src/acpi/Kconfig"
388 # This option is for the current boards/chipsets where SPI flash
389 # is not the boot device. Currently nearly all boards/chipsets assume
390 # SPI flash is the boot device.
391 config BOOT_DEVICE_NOT_SPI_FLASH
395 config BOOT_DEVICE_SPI_FLASH
397 default y if !BOOT_DEVICE_NOT_SPI_FLASH
400 config BOOT_DEVICE_MEMORY_MAPPED
402 default y if ARCH_X86 && BOOT_DEVICE_SPI_FLASH
405 Inform system if SPI is memory-mapped or not.
407 config BOOT_DEVICE_SUPPORTS_WRITES
411 Indicate that the platform has writable boot device
424 default 0x1000 if ARCH_X86
431 source "src/console/Kconfig"
433 config HAVE_ACPI_RESUME
437 config ACPI_HUGE_LOWMEM_BACKUP
441 On S3 resume path, backup low memory from RAMBASE..RAMTOP in CBMEM.
443 config RESUME_PATH_SAME_AS_BOOT
445 default y if ARCH_X86
446 depends on HAVE_ACPI_RESUME
448 This option indicates that when a system resumes it takes the
449 same path as a regular boot. e.g. an x86 system runs from the
450 reset vector at 0xfffffff0 on both resume and warm/cold boot.
452 config HAVE_HARD_RESET
456 This variable specifies whether a given board has a hard_reset
457 function, no matter if it's provided by board code or chipset code.
459 config HAVE_ROMSTAGE_CONSOLE_SPINLOCK
461 depends on EARLY_CBMEM_INIT
464 config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
466 depends on EARLY_CBMEM_INIT
469 This should be enabled on certain plaforms, such as the AMD
470 SR565x, that cannot handle concurrent CBFS accesses from
471 multiple APs during early startup.
473 config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK
475 depends on EARLY_CBMEM_INIT
478 config HAVE_MONOTONIC_TIMER
481 The board/chipset provides a monotonic timer.
483 config GENERIC_UDELAY
485 depends on HAVE_MONOTONIC_TIMER
487 The board/chipset uses a generic udelay function utilizing the
492 depends on HAVE_MONOTONIC_TIMER
494 Provide a timer queue for performing time-based callbacks.
496 config COOP_MULTITASKING
498 depends on TIMER_QUEUE && ARCH_X86
500 Cooperative multitasking allows callbacks to be multiplexed on the
501 main thread of ramstage. With this enabled it allows for multiple
502 execution paths to take place when they have udelay() calls within
508 depends on COOP_MULTITASKING
510 How many execution threads to cooperatively multitask with.
512 config HAVE_OPTION_TABLE
516 This variable specifies whether a given board has a cmos.layout
517 file containing NVRAM/CMOS bit definitions.
518 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
524 config HAVE_SMI_HANDLER
528 config PCI_IO_CFG_EXT
536 config USE_WATCHDOG_ON_BOOT
544 Enable Unified Memory Architecture for graphics.
546 config HAVE_ACPI_TABLES
549 This variable specifies whether a given board has ACPI table support.
550 It is usually set in mainboard/*/Kconfig.
555 This variable specifies whether a given board has MP table support.
556 It is usually set in mainboard/*/Kconfig.
557 Whether or not the MP table is actually generated by coreboot
558 is configurable by the user via GENERATE_MP_TABLE.
560 config HAVE_PIRQ_TABLE
563 This variable specifies whether a given board has PIRQ table support.
564 It is usually set in mainboard/*/Kconfig.
565 Whether or not the PIRQ table is actually generated by coreboot
566 is configurable by the user via GENERATE_PIRQ_TABLE.
568 config MAX_PIRQ_LINKS
572 This variable specifies the number of PIRQ interrupt links which are
573 routable. On most chipsets, this is 4, INTA through INTD. Some
574 chipsets offer more than four links, commonly up to INTH. They may
575 also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
576 table specifies links greater than 4, pirq_route_irqs will not
577 function properly, unless this variable is correctly set.
587 Build support for NHLT (non HD Audio) ACPI table generation.
591 depends on HAVE_ACPI_TABLES
593 Build an ACPI Boot Error Record Table.
595 #These Options are here to avoid "undefined" warnings.
596 #The actual selection and help texts are in the following menu.
600 config GENERATE_MP_TABLE
601 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
603 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
605 Generate an MP table (conforming to the Intel MultiProcessor
606 specification 1.4) for this board.
610 config GENERATE_PIRQ_TABLE
611 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
613 default HAVE_PIRQ_TABLE
615 Generate a PIRQ table for this board.
619 config GENERATE_SMBIOS_TABLES
621 bool "Generate SMBIOS tables"
624 Generate SMBIOS tables for this board.
628 config SMBIOS_PROVIDED_BY_MOBO
632 config MAINBOARD_SERIAL_NUMBER
633 string "SMBIOS Serial Number"
634 depends on GENERATE_SMBIOS_TABLES
635 depends on !SMBIOS_PROVIDED_BY_MOBO
638 The Serial Number to store in SMBIOS structures.
640 config MAINBOARD_VERSION
641 string "SMBIOS Version Number"
642 depends on GENERATE_SMBIOS_TABLES
643 depends on !SMBIOS_PROVIDED_BY_MOBO
646 The Version Number to store in SMBIOS structures.
648 config MAINBOARD_SMBIOS_MANUFACTURER
649 string "SMBIOS Manufacturer"
650 depends on GENERATE_SMBIOS_TABLES
651 depends on !SMBIOS_PROVIDED_BY_MOBO
652 default MAINBOARD_VENDOR
654 Override the default Manufacturer stored in SMBIOS structures.
656 config MAINBOARD_SMBIOS_PRODUCT_NAME
657 string "SMBIOS Product name"
658 depends on GENERATE_SMBIOS_TABLES
659 depends on !SMBIOS_PROVIDED_BY_MOBO
660 default MAINBOARD_PART_NUMBER
662 Override the default Product name stored in SMBIOS structures.
664 config SMBIOS_ENCLOSURE_TYPE
666 depends on GENERATE_SMBIOS_TABLES
667 default 0x09 if SYSTEM_TYPE_LAPTOP
670 System Enclosure or Chassis Types as defined in SMBIOS specification.
671 The default value is SMBIOS_ENCLOSURE_DESKTOP (0x03) or
672 SMBIOS_ENCLOSURE_LAPTOP (0x09) if SYSTEM_TYPE_LAPTOP is set.
676 source "payloads/Kconfig"
680 # TODO: Better help text and detailed instructions.
682 bool "GDB debugging support"
684 depends on CONSOLE_SERIAL
686 If enabled, you will be able to set breakpoints for gdb debugging.
687 See src/arch/x86/lib/c_start.S for details.
690 bool "Wait for a GDB connection in the ramstage"
694 If enabled, coreboot will wait for a GDB connection in the ramstage.
698 bool "Halt when hitting a BUG() or assertion error"
701 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
704 bool "Output verbose CBFS debug messages"
707 This option enables additional CBFS related debug messages.
709 config HAVE_DEBUG_RAM_SETUP
712 config DEBUG_RAM_SETUP
713 bool "Output verbose RAM init debug messages"
715 depends on HAVE_DEBUG_RAM_SETUP
717 This option enables additional RAM init related debug messages.
718 It is recommended to enable this when debugging issues on your
719 board which might be RAM init related.
721 Note: This option will increase the size of the coreboot image.
725 config HAVE_DEBUG_CAR
730 depends on HAVE_DEBUG_CAR
732 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
733 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
734 # printk(BIOS_DEBUG, ...) calls.
736 bool "Output verbose Cache-as-RAM debug messages"
738 depends on HAVE_DEBUG_CAR
740 This option enables additional CAR related debug messages.
744 bool "Check PIRQ table consistency"
746 depends on GENERATE_PIRQ_TABLE
750 config HAVE_DEBUG_SMBUS
754 bool "Output verbose SMBus debug messages"
756 depends on HAVE_DEBUG_SMBUS
758 This option enables additional SMBus (and SPD) debug messages.
760 Note: This option will increase the size of the coreboot image.
765 bool "Output verbose SMI debug messages"
767 depends on HAVE_SMI_HANDLER
768 select SPI_FLASH_SMM if SPI_CONSOLE || CONSOLE_SPI_FLASH
770 This option enables additional SMI related debug messages.
772 Note: This option will increase the size of the coreboot image.
776 config DEBUG_SMM_RELOCATION
777 bool "Debug SMM relocation code"
779 depends on HAVE_SMI_HANDLER
781 This option enables additional SMM handler relocation related
784 Note: This option will increase the size of the coreboot image.
788 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
789 # printk(BIOS_DEBUG, ...) calls.
791 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
795 This option enables additional malloc related debug messages.
797 Note: This option will increase the size of the coreboot image.
801 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
802 # printk(BIOS_DEBUG, ...) calls.
804 prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
808 This option enables additional ACPI related debug messages.
810 Note: This option will slightly increase the size of the coreboot image.
814 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
815 # printk(BIOS_DEBUG, ...) calls.
816 config REALMODE_DEBUG
817 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
820 depends on PCI_OPTION_ROM_RUN_REALMODE
822 This option enables additional x86emu related debug messages.
824 Note: This option will increase the time to emulate a ROM.
829 bool "Output verbose x86emu debug messages"
831 depends on PCI_OPTION_ROM_RUN_YABEL
833 This option enables additional x86emu related debug messages.
835 Note: This option will increase the size of the coreboot image.
839 config X86EMU_DEBUG_JMP
840 bool "Trace JMP/RETF"
842 depends on X86EMU_DEBUG
844 Print information about JMP and RETF opcodes from x86emu.
846 Note: This option will increase the size of the coreboot image.
850 config X86EMU_DEBUG_TRACE
851 bool "Trace all opcodes"
853 depends on X86EMU_DEBUG
855 Print _all_ opcodes that are executed by x86emu.
857 WARNING: This will produce a LOT of output and take a long time.
859 Note: This option will increase the size of the coreboot image.
863 config X86EMU_DEBUG_PNP
864 bool "Log Plug&Play accesses"
866 depends on X86EMU_DEBUG
868 Print Plug And Play accesses made by option ROMs.
870 Note: This option will increase the size of the coreboot image.
874 config X86EMU_DEBUG_DISK
877 depends on X86EMU_DEBUG
879 Print Disk I/O related messages.
881 Note: This option will increase the size of the coreboot image.
885 config X86EMU_DEBUG_PMM
888 depends on X86EMU_DEBUG
890 Print messages related to POST Memory Manager (PMM).
892 Note: This option will increase the size of the coreboot image.
897 config X86EMU_DEBUG_VBE
898 bool "Debug VESA BIOS Extensions"
900 depends on X86EMU_DEBUG
902 Print messages related to VESA BIOS Extension (VBE) functions.
904 Note: This option will increase the size of the coreboot image.
908 config X86EMU_DEBUG_INT10
909 bool "Redirect INT10 output to console"
911 depends on X86EMU_DEBUG
913 Let INT10 (i.e. character output) calls print messages to debug output.
915 Note: This option will increase the size of the coreboot image.
919 config X86EMU_DEBUG_INTERRUPTS
920 bool "Log intXX calls"
922 depends on X86EMU_DEBUG
924 Print messages related to interrupt handling.
926 Note: This option will increase the size of the coreboot image.
930 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
931 bool "Log special memory accesses"
933 depends on X86EMU_DEBUG
935 Print messages related to accesses to certain areas of the virtual
936 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
938 Note: This option will increase the size of the coreboot image.
942 config X86EMU_DEBUG_MEM
943 bool "Log all memory accesses"
945 depends on X86EMU_DEBUG
947 Print memory accesses made by option ROM.
948 Note: This also includes accesses to fetch instructions.
950 Note: This option will increase the size of the coreboot image.
954 config X86EMU_DEBUG_IO
955 bool "Log IO accesses"
957 depends on X86EMU_DEBUG
959 Print I/O accesses made by option ROM.
961 Note: This option will increase the size of the coreboot image.
965 config X86EMU_DEBUG_TIMINGS
966 bool "Output timing information"
968 depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER
970 Print timing information needed by i915tool.
974 config DEBUG_SPI_FLASH
975 bool "Output verbose SPI flash debug messages"
979 This option enables additional SPI flash related debug messages.
981 config DEBUG_USBDEBUG
982 bool "Output verbose USB 2.0 EHCI debug dongle messages"
986 This option enables additional USB 2.0 debug dongle related messages.
988 Select this to debug the connection of usbdebug dongle. Note that
989 you need some other working console to receive the messages.
991 if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
992 # Only visible with the right southbridge and loglevel.
993 config DEBUG_INTEL_ME
994 bool "Verbose logging for Intel Management Engine"
997 Enable verbose logging for Intel Management Engine driver that
998 is present on Intel 6-series chipsets.
1002 bool "Trace function calls"
1005 If enabled, every function will print information to console once
1006 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
1007 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
1008 of calling function. Please note some printk related functions
1009 are omitted from trace to have good looking console dumps.
1011 config DEBUG_COVERAGE
1012 bool "Debug code coverage"
1016 If enabled, the code coverage hooks in coreboot will output some
1017 information about the coverage data that is dumped.
1019 config DEBUG_BOOT_STATE
1020 bool "Debug boot state machine"
1023 Control debugging of the boot state machine. When selected displays
1024 the state boundaries in ramstage.
1026 config DEBUG_ADA_CODE
1027 bool "Compile debug code in Ada sources"
1030 Add the compiler switch `-gnata` to compile code guarded by
1033 config HAVE_EM100_SUPPORT
1034 bool "Platform can support the Dediprog EM100 SPI emulator"
1036 This is enabled by platforms which can support using the EM100.
1039 bool "Configure image for EM100 usage"
1040 depends on HAVE_EM100_SUPPORT
1042 The Dediprog EM100 SPI emulator allows fast loading of new SPI images
1043 over USB. However it only supports a maximum SPI clock of 20MHz and
1044 single data output. Enable this option to use a 20MHz SPI clock and
1045 disable "Dual Output Fast Read" Support.
1047 On AMD platforms this changes the SPI speed at run-time if the
1048 mainboard code supports this. On supported Intel platforms this works
1049 by changing the settings in the descriptor.bin file.
1054 ###############################################################################
1055 # Set variables with no prompt - these can be set anywhere, and putting at
1056 # the end of this file gives the most flexibility.
1058 source "src/lib/Kconfig"
1060 config ENABLE_APIC_EXT_ID
1064 config WARNINGS_ARE_ERRORS
1068 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1069 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1070 # mutually exclusive. One of these options must be selected in the
1071 # mainboard Kconfig if the chipset supports enabling and disabling of
1072 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1073 # in mainboard/Kconfig to know if the button should be enabled or not.
1075 config POWER_BUTTON_DEFAULT_ENABLE
1078 Select when the board has a power button which can optionally be
1079 disabled by the user.
1081 config POWER_BUTTON_DEFAULT_DISABLE
1084 Select when the board has a power button which can optionally be
1085 enabled by the user, e.g. when the board ships with a jumper over
1086 the power switch contacts.
1088 config POWER_BUTTON_FORCE_ENABLE
1091 Select when the board requires that the power button is always
1094 config POWER_BUTTON_FORCE_DISABLE
1097 Select when the board requires that the power button is always
1098 disabled, e.g. when it has been hardwired to ground.
1100 config POWER_BUTTON_IS_OPTIONAL
1102 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1103 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1105 Internal option that controls ENABLE_POWER_BUTTON visibility.
1111 Internal option that controls whether we compile in register scripts.
1113 config MAX_REBOOT_CNT
1117 Internal option that sets the maximum number of bootblock executions allowed
1118 with the normal image enabled before assuming the normal image is defective
1119 and switching to the fallback image.
1121 config CREATE_BOARD_CHECKLIST
1125 When selected, creates a webpage showing the implementation status for
1126 the board. Routines highlighted in green are complete, yellow are
1127 optional and red are required and must be implemented. A table is
1128 produced for each stage of the boot process except the bootblock. The
1129 red items may be used as an implementation checklist for the board.
1131 config MAKE_CHECKLIST_PUBLIC
1135 When selected, build/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html
1136 is copied into the Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board
1139 config CHECKLIST_DATA_FILE_LOCATION
1142 Location of the <stage>_complete.dat and <stage>_optional.dat files
1143 that are consumed during checklist processing. <stage>_complete.dat
1144 contains the symbols that are expected to be in the resulting image.
1145 <stage>_optional.dat is a subset of <stage>_complete.dat and contains
1146 a list of weak symbols which the resulting image may consume. Other
1147 symbols contained only in <stage>_complete.dat will be flagged as
1148 required and not implemented if a weak implementation is found in the
1151 config UNCOMPRESSED_RAMSTAGE
1154 config NO_XIP_EARLY_STAGES
1156 default n if ARCH_X86
1159 Identify if early stages are eXecute-In-Place(XIP).
1161 config EARLY_CBMEM_INIT
1162 def_bool !LATE_CBMEM_INIT
1164 config EARLY_CBMEM_LIST
1168 Enable display of CBMEM during romstage and postcar.
1170 config RELOCATABLE_MODULES
1173 If RELOCATABLE_MODULES is selected then support is enabled for
1174 building relocatable modules in the RAM stage. Those modules can be
1175 loaded anywhere and all the relocations are handled automatically.
1177 config NO_STAGE_CACHE
1179 default y if !HAVE_ACPI_RESUME
1181 Do not save any component in stage cache for resume path. On resume,
1182 all components would be read back from CBFS again.
1184 config GENERIC_GPIO_LIB
1187 If enabled, compile the generic GPIO library. A "generic" GPIO
1188 implies configurability usually found on SoCs, particularly the
1189 ability to control internal pull resistors.
1191 config GENERIC_SPD_BIN
1194 If enabled, add support for adding spd.hex files in cbfs as spd.bin
1195 and locating it runtime to load SPD. Additionally provide provision to
1196 fetch SPD over SMBus.
1201 depends on GENERIC_SPD_BIN
1203 Total number of memory DIMM slots available on motherboard.
1204 It is multiplication of number of channel to number of DIMMs per
1207 config DIMM_SPD_SIZE
1211 Total SPD size that will be used for DIMM.
1212 Ex: DDR3 256, DDR4 512.
1214 config SPD_READ_BY_WORD
1217 config BOOTBLOCK_CUSTOM
1218 # To be selected by arch, SoC or mainboard if it does not want use the normal
1219 # src/lib/bootblock.c#main() C entry point.
1222 config C_ENVIRONMENT_BOOTBLOCK
1223 # To be selected by arch or platform if a C environment is available during the
1224 # bootblock. Normally this signifies availability of RW memory (e.g. SRAM).
1227 ###############################################################################
1228 # Set default values for symbols created before mainboards. This allows the
1229 # option to be displayed in the general menu, but the default to be loaded in
1230 # the mainboard if desired.
1231 config COMPRESS_RAMSTAGE
1232 default y if !UNCOMPRESSED_RAMSTAGE
1234 config COMPRESS_PRERAM_STAGES
1235 depends on !ARCH_X86
1238 config INCLUDE_CONFIG_FILE
1241 config BOOTSPLASH_FILE
1242 depends on BOOTSPLASH_IMAGE
1243 default "bootsplash.jpg"