src/mainboard/jetway/nf81-t56n-lf/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <amdblocks/acpimmio.h>
   4 #include <device/mmio.h>
   5 #include <device/device.h>
   6
   7 #include <southbridge/amd/common/amd_pci_util.h>
   8 #include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
   9 #include <southbridge/amd/cimx/sb800/pci_devs.h>
  10 #include <northbridge/amd/agesa/family14/pci_devs.h>
  11
  12 /***********************************************************
  13  * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
  14  * This table is responsible for physically routing the PIC and
  15  * IOAPIC IRQs to the different PCI devices on the system.  It
  16  * is read and written via registers 0xC00/0xC01 as an
  17  * Index/Data pair.  These values are chipset and mainboard
  18  * dependent and should be updated accordingly.
  19  *
  20  * These values are used by the PCI configuration space,
  21  * MP Tables.  TODO: Make ACPI use these values too.
  22  *
  23  * The Persimmon PCI INTA/B/C/D pins are connected to
  24  * FCH pins INTE/F/G/H on the schematic so these need
  25  * to be routed as well.
  26  */
  27 static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
  28         /* INTA# - INTH# */
  29         [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
  30         /* Misc-nil,0,1,2, INT from Serial irq */
  31         [0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
  32         /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */
  33         [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F,
  34         /* IMC INT0 - 5 */
  35         [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
  36         /* USB Devs 18/19/20/22 INTA-C */
  37         [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,
  38         /* IDE, SATA */
  39         [0x40] = 0x0B,0x0B,
  40         /* GPPInt0 - 3 */
  41         [0x50] = 0x0A,0x0B,0x0A,0x0B
  42 };
  43
  44 static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
  45         /* INTA# - INTH# */
  46         [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
  47         /* Misc-nil,0,1,2, INT from Serial irq */
  48         [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
  49         /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */
  50         [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,
  51         /* IMC INT0 - 5 */
  52         [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
  53         /* USB Devs 18/19/22/20 INTA-C */
  54         [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,
  55         /* IDE, SATA */
  56         [0x40] = 0x11,0x13,
  57         /* GPPInt0 - 3 */
  58         [0x50] = 0x10,0x11,0x12,0x13
  59 };
  60
  61 /*
  62  * This table defines the index into the picr/intr_data
  63  * tables for each device.  Any enabled device and slot
  64  * that uses hardware interrupts should have an entry
  65  * in this table to define its index into the FCH
  66  * PCI_INTR register 0xC00/0xC01.  This index will define
  67  * the interrupt that it should use.  Putting PIRQ_A into
  68  * the PIN A index for a device will tell that device to
  69  * use PIC IRQ 10 if it uses PIN A for its hardware INT.
  70  */
  71 /*
  72  * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H
  73  * but because PCI INT_PIN swizzling isn't implemented to match
  74  * the IDSEL (dev 3) of the slot, the table is adjusted for the
  75  * swizzle and INTA is connected to PIRQH so PINA/B/C/D on
  76  * off-chip devices should get mapped to PIRQH/E/F/G.
  77  */
  78 static const struct pirq_struct mainboard_pirq_data[] = {
  79         /* {PCI_devfn,        {PIN A, PIN B, PIN C, PIN D}}, */
  80         {GFX_DEVFN,           {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}},      /* VGA:       01.0 */
  81         {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* NIC:       04.0 */
  82         {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* PCIe bdg:  06.0 */
  83         {SATA_DEVFN,          {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},  /* SATA:      11.0 */
  84         {OHCI1_DEVFN,         {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1:     12.0 */
  85         {EHCI1_DEVFN,         {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1:     12.2 */
  86         {OHCI2_DEVFN,         {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2:     13.0 */
  87         {EHCI2_DEVFN,         {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2:     13.2 */
  88         {SMBUS_DEVFN,         {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS:     14.0 */
  89         {IDE_DEVFN,           {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}},   /* IDE:       14.1 */
  90         {HDA_DEVFN,           {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},   /* HDA:       14.2 */
  91         {SB_PCI_PORT_DEVFN,   {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}},        /* PCI bdg:   14.4 */
  92         {OHCI4_DEVFN,         {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4:     14.5 */
  93         {OHCI3_DEVFN,         {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3:     16.0 */
  94         {EHCI3_DEVFN,         {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3:     16.2 */
  95 };
  96
  97 /* PIRQ Setup */
  98 static void pirq_setup(void)
  99 {
 100         pirq_data_ptr = mainboard_pirq_data;
 101         pirq_data_size = ARRAY_SIZE(mainboard_pirq_data);
 102         intr_data_ptr = mainboard_intr_data;
 103         picr_data_ptr = mainboard_picr_data;
 104 }
 105
 106 /**********************************************
 107  * Enable the dedicated functions of the board.
 108  **********************************************/
 109 static void mainboard_enable(struct device *dev)
 110 {
 111         /* enable GPP CLK0 thru CLK3 (interleaved) */
 112         /* disable GPP CLK4 thru SLT_GFX_CLK */
 113         misc_write8(0, 0xff);
 114         misc_write8(1, 0xff);
 115         misc_write8(2, 0);
 116         misc_write8(3, 0);
 117         misc_write8(4, 0);
 118
 119         /*
 120          * Initialize ASF registers to an arbitrary address because someone
 121          * long ago set things up this way inside the SPD read code. The
 122          * SPD read code has been made generic and moved out of the board
 123          * directory, so the ASF init is being done here.
 124          */
 125         pm_write8(0x29, 0x80);
 126         pm_write8(0x28, 0x61);
 127
 128         /* Initialize the PIRQ data structures for consumption */
 129         pirq_setup();
 130 }
 131
 132 struct chip_operations mainboard_ops = {
 133         .enable_dev = mainboard_enable,
 134 };