util/msrtool/via_c7.c

   1 /* This file is part of msrtool. */
   2 /* SPDX-License-Identifier: GPL-2.0-only */
   3
   4 #include "msrtool.h"
   5
   6 int via_c7_probe(const struct targetdef *target, const struct cpuid_t *id) {
   7         return ((VENDOR_CENTAUR == id->vendor) &&
   8                 (0x6 == id->family) && (
   9                 (0xa == id->model) || /* C7 A */
  10                 (0xd == id->model) || /* C7 D */
  11                 (0xf == id->model)    /* Nano */
  12                 ));
  13 }
  14
  15 const struct msrdef via_c7_msrs[] = {
  16         {0x10, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STAMP_COUNTER", "", {
  17                 { BITS_EOT }
  18         }},
  19         {0x2a, MSRTYPE_RDWR, MSR2(0, 0), "EBL_CR_POWERON", "", {
  20                 { BITS_EOT }
  21         }},
  22         {0xc1, MSRTYPE_RDWR, MSR2(0, 0), "PERFCTR0", "", {
  23                 { BITS_EOT }
  24         }},
  25         {0xc2, MSRTYPE_RDWR, MSR2(0, 0), "PERFCTR1", "", {
  26                 { BITS_EOT }
  27         }},
  28         {0x11e, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_CTL3", "", {
  29                 { BITS_EOT }
  30         }},
  31         /* if CPUID.0AH: EAX[15:8] > 0 */
  32         {0x186, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERFEVTSEL0",
  33                         "Performance Event Select Register 0", {
  34                 { 63, 32, RESERVED },
  35                 { 31, 8, "CMASK", "R/W", PRESENT_HEX, {
  36                         /* When CMASK is not zero, the corresponding performance
  37                          * counter 0 increments each cycle if the event count
  38                          * is greater than or equal to the CMASK.
  39                          */
  40                         { BITVAL_EOT }
  41                 }},
  42                 { 23, 1, "INV", "R/W", PRESENT_BIN, {
  43                         { MSR1(0), "CMASK using as is" },
  44                         { MSR1(1), "CMASK inerting" },
  45                         { BITVAL_EOT }
  46                 }},
  47                 { 22, 1, "EN", "R/W", PRESENT_BIN, {
  48                         { MSR1(0), "No commence counting" },
  49                         { MSR1(1), "Commence counting" },
  50                         { BITVAL_EOT }
  51                 }},
  52                 { 21, 1, "AnyThread", "R/W", PRESENT_BIN, {
  53                         { BITVAL_EOT }
  54                 }},
  55                 { 20, 1, "INT", "R/W", PRESENT_BIN, {
  56                         { MSR1(0), "Interrupt on counter overflow is disabled" },
  57                         { MSR1(1), "Interrupt on counter overflow is enabled" },
  58                         { BITVAL_EOT }
  59                 }},
  60                 { 19, 1, "PC", "R/W", PRESENT_BIN, {
  61                         { MSR1(0), "Disabled pin control" },
  62                         { MSR1(1), "Enabled pin control" },
  63                         { BITVAL_EOT }
  64                 }},
  65                 { 18, 1, "Edge", "R/W", PRESENT_BIN, {
  66                         { MSR1(0), "Disabled edge detection" },
  67                         { MSR1(1), "Enabled edge detection" },
  68                         { BITVAL_EOT }
  69                 }},
  70                 { 17, 1, "OS", "R/W", PRESENT_BIN, {
  71                         { MSR1(0), "Nothing" },
  72                         { MSR1(1), "Counts while in privilege level is ring 0" },
  73                         { BITVAL_EOT }
  74                 }},
  75                 { 16, 1, "USR", "R/W", PRESENT_BIN, {
  76                         { MSR1(0), "Nothing" },
  77                         { MSR1(1), "Counts while in privilege level is not ring 0" },
  78                         { BITVAL_EOT }
  79                 }},
  80                 { 15, 8, "UMask", "R/W", PRESENT_HEX, {
  81                         /* Qualifies the microarchitectural condition
  82                          * to detect on the selected event logic. */
  83                         { BITVAL_EOT }
  84                 }},
  85                 { 7, 8, "Event Select", "R/W", PRESENT_HEX, {
  86                         /* Selects a performance event logic unit. */
  87                         { BITVAL_EOT }
  88                 }},
  89                 { BITS_EOT }
  90         }},
  91         /* if CPUID.0AH: EAX[15:8] > 0 */
  92         {0x187, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERFEVTSEL1",
  93                         "Performance Event Select Register 1", {
  94                 { 63, 32, RESERVED },
  95                 { 31, 8, "CMASK", "R/W", PRESENT_HEX, {
  96                         /* When CMASK is not zero, the corresponding performance
  97                          * counter 1 increments each cycle if the event count
  98                          * is greater than or equal to the CMASK.
  99                          */
 100                         { BITVAL_EOT }
 101                 }},
 102                 { 23, 1, "INV", "R/W", PRESENT_BIN, {
 103                         { MSR1(0), "CMASK using as is" },
 104                         { MSR1(1), "CMASK inerting" },
 105                         { BITVAL_EOT }
 106                 }},
 107                 { 22, 1, "EN", "R/W", PRESENT_BIN, {
 108                         { MSR1(0), "No commence counting" },
 109                         { MSR1(1), "Commence counting" },
 110                         { BITVAL_EOT }
 111                 }},
 112                 { 21, 1, "AnyThread", "R/W", PRESENT_BIN, {
 113                         { BITVAL_EOT }
 114                 }},
 115                 { 20, 1, "INT", "R/W", PRESENT_BIN, {
 116                         { MSR1(0), "Interrupt on counter overflow is disabled" },
 117                         { MSR1(1), "Interrupt on counter overflow is enabled" },
 118                         { BITVAL_EOT }
 119                 }},
 120                 { 19, 1, "PC", "R/W", PRESENT_BIN, {
 121                         { MSR1(0), "Disabled pin control" },
 122                         { MSR1(1), "Enabled pin control" },
 123                         { BITVAL_EOT }
 124                 }},
 125                 { 18, 1, "Edge", "R/W", PRESENT_BIN, {
 126                         { MSR1(0), "Disabled edge detection" },
 127                         { MSR1(1), "Enabled edge detection" },
 128                         { BITVAL_EOT }
 129                 }},
 130                 { 17, 1, "OS", "R/W", PRESENT_BIN, {
 131                         { MSR1(0), "Nothing" },
 132                         { MSR1(1), "Counts while in privilege level is ring 0" },
 133                         { BITVAL_EOT }
 134                 }},
 135                 { 16, 1, "USR", "R/W", PRESENT_BIN, {
 136                         { MSR1(0), "Nothing" },
 137                         { MSR1(1), "Counts while in privilege level is not ring 0" },
 138                         { BITVAL_EOT }
 139                 }},
 140                 { 15, 8, "UMask", "R/W", PRESENT_HEX, {
 141                         /* Qualifies the microarchitectural condition
 142                          * to detect on the selected event logic. */
 143                         { BITVAL_EOT }
 144                 }},
 145                 { 7, 8, "Event Select", "R/W", PRESENT_HEX, {
 146                         /* Selects a performance event logic unit. */
 147                         { BITVAL_EOT }
 148                 }},
 149                 { BITS_EOT }
 150         }},
 151         {0x198, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_STATUS", "", {
 152                 { 63, 8, "Lowest Supported Clock Ratio", "R/O", PRESENT_HEX, {
 153                         { BITVAL_EOT }
 154                 }},
 155                 { 55, 8, "Lowest Supported Voltage", "R/O", PRESENT_HEX, {
 156                         { BITVAL_EOT }
 157                 }},
 158                 { 47, 8, "Highest Supported Clock Ratio", "R/O", PRESENT_HEX, {
 159                         { BITVAL_EOT }
 160                 }},
 161                 { 39, 8, "Highest Supported Voltage", "R/O", PRESENT_HEX, {
 162                         { BITVAL_EOT }
 163                 }},
 164                 { 31, 8, "Lowest Clock Ratio", "R/O", PRESENT_HEX, {
 165                         { BITVAL_EOT }
 166                 }},
 167                 { 23, 2, RESERVED },
 168                 { 21, 2, "Performance Control MSR Transition", "R/O", PRESENT_HEX, {
 169                         { BITVAL_EOT }
 170                 }},
 171                 { 19, 1, "Thermal Monitor 2 transition", "R/O", PRESENT_BIN, {
 172                         { BITVAL_EOT }
 173                 }},
 174                 { 18, 1, "Thermal Monitor 2 transition", "R/O", PRESENT_BIN, {
 175                         { BITVAL_EOT }
 176                 }},
 177                 { 17, 1, "Voltage Transition in progress", "R/O", PRESENT_BIN, {
 178                         { BITVAL_EOT }
 179                 }},
 180                 { 16, 1, "Clock Ratio Transition in progress", "R/O", PRESENT_BIN, {
 181                         { BITVAL_EOT }
 182                 }},
 183                 { 15, 8, "Current Clock Ratio", "R/W", PRESENT_HEX, {
 184                         { BITVAL_EOT }
 185                 }},
 186                 { 7, 8, "16*x + 700 = Current voltage in mV", "R/W", PRESENT_HEX, {
 187                         { BITVAL_EOT }
 188                 }},
 189                 { BITS_EOT }
 190         }},
 191         {0x199, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_CTL", "", {
 192                 { 63, 48, RESERVED },
 193                 { 15, 8, "Desired Clock Ratio", "R/W", PRESENT_HEX, {
 194                         { BITVAL_EOT }
 195                 }},
 196                 { 7, 8, "16*x + 700 = Desired voltage in mV", "R/W", PRESENT_HEX, {
 197                         { BITVAL_EOT }
 198                 }},
 199                 { BITS_EOT }
 200         }},
 201         {0x19a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_CLOCK_MODULATION", "", {
 202                 { 63, 59, RESERVED },
 203                 { 15, 8, "allows selection of the on-demand clock modulation duty cycle", "R/W", PRESENT_BIN, {
 204                         { MSR1(0), "Reserved" },
 205                         { MSR1(1), "12.5%" },
 206                         { MSR1(2), "25.0%" },
 207                         { MSR1(3), "37.5%" },
 208                         { MSR1(4), "50.0%" },
 209                         { MSR1(5), "62.5%" },
 210                         { MSR1(6), "75.0%" },
 211                         { MSR1(7), "87.5%" },
 212                         { BITVAL_EOT }
 213                 }},
 214                 { 0, 1, RESERVED },
 215                 { BITS_EOT }
 216         }},
 217         {0x19b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_INTERRUPT", "", {
 218                 { 63, 62, RESERVED },
 219                 { 1, 1, "Enables APIC LVT interrupt on a low-to-high temp transition", "R/W", PRESENT_BIN, {
 220                         { BITVAL_EOT }
 221                 }},
 222                 { 0, 1, "Enables APIC LVT interrupt on a high-to-low temp transition", "R/W", PRESENT_BIN, {
 223                         { BITVAL_EOT }
 224                 }},
 225                 { BITS_EOT }
 226         }},
 227         {0x19c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_STATUS", "", {
 228                 { 63, 62, RESERVED },
 229                 { 1, 1, "TCC assert detect", "R/O", PRESENT_BIN, {
 230                         { MSR1(0), "TCC not asserted" },
 231                         { MSR1(1), "TCC asserted" },
 232                         { BITVAL_EOT }
 233                 }},
 234                 { 0, 1, "TCC trigger detect (Sticky bit, only cleared upon reset)", "R/O", PRESENT_BIN, {
 235                         { MSR1(0), "TCC not triggered" },
 236                         { MSR1(1), "TCC triggered" },
 237                         { BITVAL_EOT }
 238                 }},
 239                 { BITS_EOT }
 240         }},
 241         {0x19d, MSRTYPE_RDWR, MSR2(0, 0), "MSR_THERM2_CTL", "", {
 242                 { 63, 47, RESERVED },
 243                 { 16, 1, "Thermal Monitor enable", "R/W", PRESENT_HEX, {
 244                         { MSR1(0), "Thermal Monitor 1 enabled" },
 245                         { MSR1(1), "Thermal Monitor 2 enabled" },
 246                         { BITVAL_EOT }
 247                 }},
 248                 { 15, 8, "Thermal Monitor 2 performance state clock ratio", "R/W", PRESENT_HEX, {
 249                         { BITVAL_EOT }
 250                 }},
 251                 { 7, 8, "Thermal Monitor 2 performance state volatege", "R/W", PRESENT_HEX, {
 252                         { BITVAL_EOT }
 253                 }},
 254                 { BITS_EOT }
 255         }},
 256         {0x1a0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MISC_ENABLES", "", {
 257                 { 63, 43, RESERVED },
 258                 { 20, 1, "PowerSaver lock", "R/W", PRESENT_BIN, {
 259                         { MSR1(0), "Bit 16 can be set and cleared." },
 260                         { MSR1(1), "Bit 16 can only be cleared upon reset." },
 261                         { BITVAL_EOT }
 262                 }},
 263                 { 19, 3, RESERVED },
 264                 { 16, 1, "Enhanced PowerSaver enable", "R/W", PRESENT_BIN, {
 265                         { MSR1(0), "Performance state changes disabled" },
 266                         { MSR1(1), "Performance state changes enabled" },
 267                         { BITVAL_EOT }
 268                 }},
 269                 { 15, 5, RESERVED },
 270                 { 10, 1, "PBE enable", "R/W", PRESENT_BIN, {
 271                         { MSR1(0), "FERR# legacy mode" },
 272                         { MSR1(1), "Enables break events for APIC via FERR#" },
 273                         { BITVAL_EOT }
 274                 }},
 275                 { 9, 6, RESERVED },
 276                 { 3, 1, "Thermal Monitor 2 enable", "R/W", PRESENT_BIN, {
 277                         { MSR1(0), "On-die clock throttling enabled" },
 278                         { MSR1(1), "Thermal Monitor 1 or 2 enabled" },
 279                         { BITVAL_EOT }
 280                 }},
 281                 { 2, 3, RESERVED },
 282                 { BITS_EOT }
 283         }},
 284         {0x200, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE0", "", {
 285                 { BITS_EOT }
 286         }},
 287         {0x201, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK0", "", {
 288                 { BITS_EOT }
 289         }},
 290         {0x202, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE1", "", {
 291                 { BITS_EOT }
 292         }},
 293         {0x203, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK1", "", {
 294                 { BITS_EOT }
 295         }},
 296         {0x204, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE2", "", {
 297                 { BITS_EOT }
 298         }},
 299         {0x205, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK2", "", {
 300                 { BITS_EOT }
 301         }},
 302         {0x206, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE3", "", {
 303                 { BITS_EOT }
 304         }},
 305         {0x207, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK3", "", {
 306                 { BITS_EOT }
 307         }},
 308         {0x208, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE4", "", {
 309                 { BITS_EOT }
 310         }},
 311         {0x209, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK4", "", {
 312                 { BITS_EOT }
 313         }},
 314         {0x20a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE5", "", {
 315                 { BITS_EOT }
 316         }},
 317         {0x20b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK5", "", {
 318                 { BITS_EOT }
 319         }},
 320         {0x20c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE6", "", {
 321                 { BITS_EOT }
 322         }},
 323         {0x20d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK6", "", {
 324                 { BITS_EOT }
 325         }},
 326         {0x20e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE7", "", {
 327                 { BITS_EOT }
 328         }},
 329         {0x20f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK7", "", {
 330                 { BITS_EOT }
 331         }},
 332         {0x250, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX64K_00000", "", {
 333                 { BITS_EOT }
 334         }},
 335         {0x258, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_80000", "", {
 336                 { BITS_EOT }
 337         }},
 338         {0x259, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_A0000", "", {
 339                 { BITS_EOT }
 340         }},
 341         {0x268, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C0000", "", {
 342                 { BITS_EOT }
 343         }},
 344         {0x269, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C8000", "", {
 345                 { BITS_EOT }
 346         }},
 347         {0x26a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D0000", "", {
 348                 { BITS_EOT }
 349         }},
 350         {0x26b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D8000", "", {
 351                 { BITS_EOT }
 352         }},
 353         {0x26c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E0000", "", {
 354                 { BITS_EOT }
 355         }},
 356         {0x26d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E8000", "", {
 357                 { BITS_EOT }
 358         }},
 359         {0x26e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F0000", "", {
 360                 { BITS_EOT }
 361         }},
 362         {0x26f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F8000", "", {
 363                 { BITS_EOT }
 364         }},
 365         {0x2ff, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_DEF_TYPE", "", {
 366                 { BITS_EOT }
 367         }},
 368         {0x1107, MSRTYPE_RDWR, MSR2(0, 0), "FCR",
 369                         "Feature Control Register", {
 370                 { 63, 55, RESERVED },
 371                 { 8, 1, "Disables L2 Cache", "R/W", PRESENT_BIN, {
 372                         { MSR1(0), "L2 Cache enabled" },
 373                         { MSR1(1), "L2 Cache disabled" },
 374                         { BITVAL_EOT }
 375                 }},
 376                 { 7, 6, RESERVED },
 377                 { 1, 1, "Enables CPUID reporting CMPXCHG8B", "R/W", PRESENT_BIN, {
 378                         { MSR1(0), "Disabled CPUID reporting CMPXCHG8B" },
 379                         { MSR1(1), "Enabled CPUID reporting CMPXCHG8B" },
 380                         { BITVAL_EOT }
 381                 }},
 382                 { 0, 1, RESERVED },
 383                 { BITS_EOT }
 384         }},
 385         {0x1108, MSRTYPE_RDWR, MSR2(0, 0), "FCR2",
 386                         "Feature Control Register 2", {
 387                 { 63, 32, "Last 4 characters of Alternate Vendor ID string", "R/W", PRESENT_STR, {
 388                         { BITVAL_EOT }
 389                 }},
 390                 { 31, 17, RESERVED },
 391                 { 14, 1, "Use the Alternate Vendor ID string", "R/W", PRESENT_BIN, {
 392                         { MSR1(0), "The CPUID instruction vendor ID is CentaurHauls" },
 393                         { MSR1(1), "The CPUID instruction returns the alternate Vendor ID" },
 394                         { BITVAL_EOT }
 395                 }},
 396                 { 13, 2, RESERVED },
 397                 { 11, 4, "Family ID", "R/W", PRESENT_HEX, {
 398                         { BITVAL_EOT }
 399                 }},
 400                 { 7, 4, "Model ID", "R/W", PRESENT_HEX, {
 401                         { BITVAL_EOT }
 402                 }},
 403                 { 3, 4, RESERVED },
 404                 { BITS_EOT }
 405         }},
 406         {0x1109, MSRTYPE_WRONLY, MSR2(0, 0), "FCR3",
 407                         "Feature Control Register 3", {
 408                 { 63, 32, "First 4 characters of Alternate Vendor ID string", "W/O", PRESENT_STR, {
 409                         { BITVAL_EOT }
 410                 }},
 411                 { 31, 32, "Middle 4 characters of Alternate Vendor ID string", "W/O", PRESENT_STR, {
 412                         { BITVAL_EOT }
 413                 }},
 414                 { BITS_EOT }
 415         }},
 416         {0x1152, MSRTYPE_RDONLY, MSR2(0, 0), "FUSES", "Fuses", {
 417                 { BITS_EOT }
 418         }},
 419         {0x1153, MSRTYPE_RDONLY, MSR2(0, 0), "BRAND",
 420                         "BRAND_1 XOR BRAND_2, (00b = C7-M, 01b = C7, 10b = Eden, 11b = Reserved)", {
 421                 { 63, 42, RESERVED },
 422                 { 21, 2, "BRAND_1", "R/O", PRESENT_BIN, {
 423                         { BITVAL_EOT }
 424                 }},
 425                 { 19, 2, "BRAND_2", "R/O", PRESENT_BIN, {
 426                         { BITVAL_EOT }
 427                 }},
 428                 { 17, 18, RESERVED },
 429                 { BITS_EOT }
 430         }},
 431         {0x1160, MSRTYPE_RDWR, MSR2(0, 0), "UNK0", "", {
 432                 { BITS_EOT }
 433         }},
 434         {0x1161, MSRTYPE_RDWR, MSR2(0, 0), "UNK1", "", {
 435                 { BITS_EOT }
 436         }},
 437         {0x1164, MSRTYPE_RDWR, MSR2(0, 0), "THERM_THRESH_LOW", "(FUSES[6:4] * 5 + 65)", {
 438                 { BITS_EOT }
 439         }},
 440         {0x1165, MSRTYPE_RDWR, MSR2(0, 0), "THERM_THRESH_HI", "(FUSES[6:4] * 5 + 65) + 5", {
 441                 { BITS_EOT }
 442         }},
 443         {0x1166, MSRTYPE_RDWR, MSR2(0, 0), "THERM_THRESH_OVERSTRESS", "", {
 444                 { BITS_EOT }
 445         }},
 446         {0x1167, MSRTYPE_RDWR, MSR2(0, 0), "THERM_THRESH_USER_TRIP", "", {
 447                 { BITS_EOT }
 448         }},
 449         {0x1168, MSRTYPE_RDWR, MSR2(0, 0), "UNK2", "", {
 450                 { BITS_EOT }
 451         }},
 452         {0x116a, MSRTYPE_RDWR, MSR2(0, 0), "UNK3", "", {
 453                 { BITS_EOT }
 454         }},
 455         {0x116b, MSRTYPE_RDWR, MSR2(0, 0), "UNK4", "", {
 456                 { BITS_EOT }
 457         }},
 458         { MSR_EOT }
 459 };