util/msrtool/intel_pentium_d.c

   1 /* This file is part of msrtool. */
   2 /* SPDX-License-Identifier: GPL-2.0-only */
   3
   4 #include "msrtool.h"
   5
   6 int intel_pentium_d_probe(const struct targetdef *target, const struct cpuid_t *id) {
   7         return ((VENDOR_INTEL == id->vendor) &&
   8                 (0xf == id->family) &&
   9                 (0x6 == id->model));
  10 }
  11
  12 const struct msrdef intel_pentium_d_msrs[] = {
  13         {0x0000, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_ADDR", "", {
  14                 { BITS_EOT }
  15         }},
  16         {0x0001, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_TYPE", "", {
  17                 { BITS_EOT }
  18         }},
  19         {0x0006, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MONITOR_FILTER_LINE_SIZE", "", {
  20                 { BITS_EOT }
  21         }},
  22         {0x0010, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STAMP_COUNTER", "", {
  23                 { BITS_EOT }
  24         }},
  25         {0x0017, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PLATFORM_ID", "", {
  26                 { BITS_EOT }
  27         }},
  28         {0x001B, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APIC_BASE", "", {
  29                 { BITS_EOT }
  30         }},
  31         {0x002A, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EBC_HARD_POWERON", "", {
  32                 { BITS_EOT }
  33         }},
  34         {0x002B, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EBC_SOFT_POWERON", "", {
  35                 { BITS_EOT }
  36         }},
  37         {0x002C, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EBC_FREQUENCY_ID", "", {
  38                 { BITS_EOT }
  39         }},
  40         {0x008B, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_SIGN_ID", "", {
  41                 { BITS_EOT }
  42         }},
  43         {0x00FE, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRRCAP", "", {
  44                 { BITS_EOT }
  45         }},
  46         {0x0174, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_CS", "", {
  47                 { BITS_EOT }
  48         }},
  49         {0x0175, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_ESP", "", {
  50                 { BITS_EOT }
  51         }},
  52         {0x0176, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_EIP", "", {
  53                 { BITS_EOT }
  54         }},
  55         {0x0179, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_CAP", "", {
  56                 { BITS_EOT }
  57         }},
  58         {0x017A, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_STATUS", "", {
  59                 { BITS_EOT }
  60         }},
  61         {0x0180, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RAX", "", {
  62                 { BITS_EOT }
  63         }},
  64         {0x0181, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RBX", "", {
  65                 { BITS_EOT }
  66         }},
  67         {0x0182, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RCX", "", {
  68                 { BITS_EOT }
  69         }},
  70         {0x0183, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RDX", "", {
  71                 { BITS_EOT }
  72         }},
  73         {0x0184, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RSI", "", {
  74                 { BITS_EOT }
  75         }},
  76         {0x0185, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RDI", "", {
  77                 { BITS_EOT }
  78         }},
  79         {0x0186, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_EVNTSEL0", "", {
  80                 { BITS_EOT }
  81         }},
  82         {0x0187, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_EVNTSEL1", "", {
  83                 { BITS_EOT }
  84         }},
  85         {0x0188, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RFLAGS", "", {
  86                 { BITS_EOT }
  87         }},
  88         {0x0189, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RIP", "", {
  89                 { BITS_EOT }
  90         }},
  91         {0x018A, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_MISC", "", {
  92                 { BITS_EOT }
  93         }},
  94         {0x0190, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R8", "", {
  95                 { BITS_EOT }
  96         }},
  97         {0x0191, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R9", "", {
  98                 { BITS_EOT }
  99         }},
 100         {0x0192, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R10", "", {
 101                 { BITS_EOT }
 102         }},
 103         {0x0193, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R11", "", {
 104                 { BITS_EOT }
 105         }},
 106         {0x0194, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R12", "", {
 107                 { BITS_EOT }
 108         }},
 109         {0x0195, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R13", "", {
 110                 { BITS_EOT }
 111         }},
 112         {0x0196, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R14", "", {
 113                 { BITS_EOT }
 114         }},
 115         {0x0197, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R15", "", {
 116                 { BITS_EOT }
 117         }},
 118         {0x0198, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_STATUS", "", {
 119                 { BITS_EOT }
 120         }},
 121         {0x0199, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_CONTROL", "", {
 122                 { BITS_EOT }
 123         }},
 124         {0x019A, MSRTYPE_RDWR, MSR2(0, 0), "IA32_CLOCK_MODULATION", "", {
 125                 { BITS_EOT }
 126         }},
 127         {0x019B, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_INTERRUPT", "", {
 128                 { BITS_EOT }
 129         }},
 130         {0x019C, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_STATUS", "", {
 131                 { BITS_EOT }
 132         }},
 133         {0x019D, MSRTYPE_RDWR, MSR2(0, 0), "GV_THERM", "", {
 134                 { BITS_EOT }
 135         }},
 136         {0x01A0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MISC_ENABLES", "", {
 137                 { BITS_EOT }
 138         }},
 139         {0x01A1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PLATFORM_BRV", "", {
 140                 { BITS_EOT }
 141         }},
 142         {0x01A2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TEMPERATURE_TARGET", "", {
 143                 { BITS_EOT }
 144         }},
 145         {0x01D7, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LER_FROM_LIP", "", {
 146                 { BITS_EOT }
 147         }},
 148         {0x01D8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LER_TO_LIP", "", {
 149                 { BITS_EOT }
 150         }},
 151         {0x01D9, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DEBUGCTL", "", {
 152                 { BITS_EOT }
 153         }},
 154         {0x01DA, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_TOS", "", {
 155                 { BITS_EOT }
 156         }},
 157         {0x0200, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE0", "", {
 158                 { BITS_EOT }
 159         }},
 160         {0x0201, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK0", "", {
 161                 { BITS_EOT }
 162         }},
 163         {0x0202, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE1", "", {
 164                 { BITS_EOT }
 165         }},
 166         {0x0203, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK1", "", {
 167                 { BITS_EOT }
 168         }},
 169         {0x0204, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE2", "", {
 170                 { BITS_EOT }
 171         }},
 172         {0x0205, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK2", "", {
 173                 { BITS_EOT }
 174         }},
 175         {0x0206, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE3", "", {
 176                 { BITS_EOT }
 177         }},
 178         {0x0207, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK3", "", {
 179                 { BITS_EOT }
 180         }},
 181         {0x0208, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE4", "", {
 182                 { BITS_EOT }
 183         }},
 184         {0x0209, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK4", "", {
 185                 { BITS_EOT }
 186         }},
 187         {0x020A, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE5", "", {
 188                 { BITS_EOT }
 189         }},
 190         {0x020B, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK5", "", {
 191                 { BITS_EOT }
 192         }},
 193         {0x020C, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE6", "", {
 194                 { BITS_EOT }
 195         }},
 196         {0x020D, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK6", "", {
 197                 { BITS_EOT }
 198         }},
 199         {0x020E, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE7", "", {
 200                 { BITS_EOT }
 201         }},
 202         {0x020F, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK7", "", {
 203                 { BITS_EOT }
 204         }},
 205         {0x0250, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX64K_00000", "", {
 206                 { BITS_EOT }
 207         }},
 208         {0x0258, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_80000", "", {
 209                 { BITS_EOT }
 210         }},
 211         {0x0259, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_A0000", "", {
 212                 { BITS_EOT }
 213         }},
 214         {0x0268, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C0000", "", {
 215                 { BITS_EOT }
 216         }},
 217         {0x0269, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C8000", "", {
 218                 { BITS_EOT }
 219         }},
 220         {0x026A, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D0000", "", {
 221                 { BITS_EOT }
 222         }},
 223         {0x026B, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D8000", "", {
 224                 { BITS_EOT }
 225         }},
 226         {0x026C, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E0000", "", {
 227                 { BITS_EOT }
 228         }},
 229         {0x026D, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E8000", "", {
 230                 { BITS_EOT }
 231         }},
 232         {0x026E, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F0000", "", {
 233                 { BITS_EOT }
 234         }},
 235         {0x026F, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F8000", "", {
 236                 { BITS_EOT }
 237         }},
 238         {0x0277, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PAT", "", {
 239                 { BITS_EOT }
 240         }},
 241         {0x02FF, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_DEF_TYPE", "", {
 242                 { BITS_EOT }
 243         }},
 244         {0x0300, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER0", "", {
 245                 { BITS_EOT }
 246         }},
 247         {0x0301, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER1", "", {
 248                 { BITS_EOT }
 249         }},
 250         {0x0302, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER2", "", {
 251                 { BITS_EOT }
 252         }},
 253         {0x0303, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER3", "", {
 254                 { BITS_EOT }
 255         }},
 256         {0x0304, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER0", "", {
 257                 { BITS_EOT }
 258         }},
 259         {0x0305, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER1", "", {
 260                 { BITS_EOT }
 261         }},
 262         {0x0306, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER2", "", {
 263                 { BITS_EOT }
 264         }},
 265         {0x0307, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER3", "", {
 266                 { BITS_EOT }
 267         }},
 268         {0x0308, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_COUNTER0", "", {
 269                 { BITS_EOT }
 270         }},
 271         {0x0309, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_COUNTER1", "", {
 272                 { BITS_EOT }
 273         }},
 274         {0x030A, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR1", "", {
 275                 { BITS_EOT }
 276         }},
 277         {0x030B, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_COUNTER3", "", {
 278                 { BITS_EOT }
 279         }},
 280         {0x030C, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER0", "", {
 281                 { BITS_EOT }
 282         }},
 283         {0x030D, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER1", "", {
 284                 { BITS_EOT }
 285         }},
 286         {0x030E, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER2", "", {
 287                 { BITS_EOT }
 288         }},
 289         {0x030F, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER3", "", {
 290                 { BITS_EOT }
 291         }},
 292         {0x0310, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER4", "", {
 293                 { BITS_EOT }
 294         }},
 295         {0x0311, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER5", "", {
 296                 { BITS_EOT }
 297         }},
 298         {0x0345, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_CAPABILITIES", "", {
 299                 { BITS_EOT }
 300         }},
 301         {0x0360, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR0", "", {
 302                 { BITS_EOT }
 303         }},
 304         {0x0361, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR1", "", {
 305                 { BITS_EOT }
 306         }},
 307         {0x0362, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR2", "", {
 308                 { BITS_EOT }
 309         }},
 310         {0x0363, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR3", "", {
 311                 { BITS_EOT }
 312         }},
 313         {0x0364, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR0", "", {
 314                 { BITS_EOT }
 315         }},
 316         {0x0365, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR1", "", {
 317                 { BITS_EOT }
 318         }},
 319         {0x0366, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR2", "", {
 320                 { BITS_EOT }
 321         }},
 322         {0x0367, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR3", "", {
 323                 { BITS_EOT }
 324         }},
 325         {0x0368, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR0", "", {
 326                 { BITS_EOT }
 327         }},
 328         {0x0369, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR1", "", {
 329                 { BITS_EOT }
 330         }},
 331         {0x036A, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR2", "", {
 332                 { BITS_EOT }
 333         }},
 334         {0x036B, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR3", "", {
 335                 { BITS_EOT }
 336         }},
 337         {0x036C, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR0", "", {
 338                 { BITS_EOT }
 339         }},
 340         {0x036D, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR1", "", {
 341                 { BITS_EOT }
 342         }},
 343         {0x036E, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR2", "", {
 344                 { BITS_EOT }
 345         }},
 346         {0x036F, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR3", "", {
 347                 { BITS_EOT }
 348         }},
 349         {0x0370, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR4", "", {
 350                 { BITS_EOT }
 351         }},
 352         {0x0371, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR5", "", {
 353                 { BITS_EOT }
 354         }},
 355         {0x03A0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BSU_ESCR0", "", {
 356                 { BITS_EOT }
 357         }},
 358         {0x03A1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BSU_ESCR1", "", {
 359                 { BITS_EOT }
 360         }},
 361         {0x03A2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FSB_ESCR0", "", {
 362                 { BITS_EOT }
 363         }},
 364         {0x03A3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FSB_ESCR1", "", {
 365                 { BITS_EOT }
 366         }},
 367         {0x03A4, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FIRM_ESCR0", "", {
 368                 { BITS_EOT }
 369         }},
 370         {0x03A5, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FIRM_ESCR1", "", {
 371                 { BITS_EOT }
 372         }},
 373         {0x03A6, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_ESCR0", "", {
 374                 { BITS_EOT }
 375         }},
 376         {0x03A7, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_ESCR1", "", {
 377                 { BITS_EOT }
 378         }},
 379         {0x03A8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_DAC_ESCR0", "", {
 380                 { BITS_EOT }
 381         }},
 382         {0x03A9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_DAC_ESCR1", "", {
 383                 { BITS_EOT }
 384         }},
 385         {0x03AA, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MOB_ESCR0", "", {
 386                 { BITS_EOT }
 387         }},
 388         {0x03AB, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MOB_ESCR1", "", {
 389                 { BITS_EOT }
 390         }},
 391         {0x03AC, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PMH_ESCR0", "", {
 392                 { BITS_EOT }
 393         }},
 394         {0x03AD, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PMH_ESCR1", "", {
 395                 { BITS_EOT }
 396         }},
 397         {0x03AE, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SAAT_ESCR0", "", {
 398                 { BITS_EOT }
 399         }},
 400         {0x03AF, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SAAT_ESCR1", "", {
 401                 { BITS_EOT }
 402         }},
 403         {0x03B0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_U2L_ESCR0", "", {
 404                 { BITS_EOT }
 405         }},
 406         {0x03B1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_U2L_ESCR1", "", {
 407                 { BITS_EOT }
 408         }},
 409         {0x03B2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_ESCR0", "", {
 410                 { BITS_EOT }
 411         }},
 412         {0x03B3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_ESCR1", "", {
 413                 { BITS_EOT }
 414         }},
 415         {0x03B4, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IS_ESCR0", "", {
 416                 { BITS_EOT }
 417         }},
 418         {0x03B5, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_ESCR1", "", {
 419                 { BITS_EOT }
 420         }},
 421         {0x03B6, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ITLB_ESCR0", "", {
 422                 { BITS_EOT }
 423         }},
 424         {0x03B7, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ITLB_ESCR1", "", {
 425                 { BITS_EOT }
 426         }},
 427         {0x03B8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR0", "", {
 428                 { BITS_EOT }
 429         }},
 430         {0x03B9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR1", "", {
 431                 { BITS_EOT }
 432         }},
 433         {0x03BA, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_ESCR0", "", {
 434                 { BITS_EOT }
 435         }},
 436         {0x03BB, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_ESCR1", "", {
 437                 { BITS_EOT }
 438         }},
 439         {0x03BC, MSRTYPE_RDWR, MSR2(0, 0), "MSR_RAT_ESCR0", "", {
 440                 { BITS_EOT }
 441         }},
 442         {0x03BD, MSRTYPE_RDWR, MSR2(0, 0), "MSR_RAT_ESCR1", "", {
 443                 { BITS_EOT }
 444         }},
 445         {0x03BE, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SSU_ESCR0", "", {
 446                 { BITS_EOT }
 447         }},
 448         {0x03C0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_ESCR0", "", {
 449                 { BITS_EOT }
 450         }},
 451         {0x03C1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_ESCR1", "", {
 452                 { BITS_EOT }
 453         }},
 454         {0x03C2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TBPU_ESCR0", "", {
 455                 { BITS_EOT }
 456         }},
 457         {0x03C3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TBPU_ESCR1", "", {
 458                 { BITS_EOT }
 459         }},
 460         {0x03C4, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TC_ESCR0", "", {
 461                 { BITS_EOT }
 462         }},
 463         {0x03C5, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TC_ESCR1", "", {
 464                 { BITS_EOT }
 465         }},
 466         {0x03C8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IX_ESCR0", "", {
 467                 { BITS_EOT }
 468         }},
 469         {0x03C9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IX_ESCR1", "", {
 470                 { BITS_EOT }
 471         }},
 472         {0x03CA, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ALF_ESCR0", "", {
 473                 { BITS_EOT }
 474         }},
 475         {0x03CB, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ALF_ESCR1", "", {
 476                 { BITS_EOT }
 477         }},
 478         {0x03CC, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR2", "", {
 479                 { BITS_EOT }
 480         }},
 481         {0x03CD, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR3", "", {
 482                 { BITS_EOT }
 483         }},
 484         {0x03E0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR4", "", {
 485                 { BITS_EOT }
 486         }},
 487         {0x03E1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR5", "", {
 488                 { BITS_EOT }
 489         }},
 490         {0x03F0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TC_PRECISE_EVENT", "", {
 491                 { BITS_EOT }
 492         }},
 493         {0x03F1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PEBS_ENABLE", "", {
 494                 { BITS_EOT }
 495         }},
 496         {0x03F2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PEBS_MATRIX_VERT", "", {
 497                 { BITS_EOT }
 498         }},
 499         {0x0400, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_CTL", "", {
 500                 { BITS_EOT }
 501         }},
 502         {0x0401, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_STATUS", "", {
 503                 { BITS_EOT }
 504         }},
 505         {0x0402, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_ADDR", "", {
 506                 { BITS_EOT }
 507         }},
 508         {0x0403, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_MISC", "", {
 509                 { BITS_EOT }
 510         }},
 511         {0x0404, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_CTL", "", {
 512                 { BITS_EOT }
 513         }},
 514         {0x0405, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_STATUS", "", {
 515                 { BITS_EOT }
 516         }},
 517         {0x0406, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_ADDR", "", {
 518                 { BITS_EOT }
 519         }},
 520         {0x0408, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_CTL", "", {
 521                 { BITS_EOT }
 522         }},
 523         {0x0409, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_STATUS", "", {
 524                 { BITS_EOT }
 525         }},
 526         {0x040C, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_CTL", "", {
 527                 { BITS_EOT }
 528         }},
 529         {0x040D, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_STATUS", "", {
 530                 { BITS_EOT }
 531         }},
 532         {0x040E, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_ADDR", "", {
 533                 { BITS_EOT }
 534         }},
 535         {0x040F, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_MISC", "", {
 536                 { BITS_EOT }
 537         }},
 538         {0x0600, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DS_AREA", "", {
 539                 { BITS_EOT }
 540         }},
 541         { MSR_EOT }
 542 };