util/msrtool/intel_core2_early.c

   1 /* This file is part of msrtool. */
   2 /* SPDX-License-Identifier: GPL-2.0-only */
   3
   4 #include "msrtool.h"
   5
   6 int intel_core2_early_probe(const struct targetdef *target, const struct cpuid_t *id) {
   7         return ((VENDOR_INTEL == id->vendor) &&
   8                 (0x6 == id->family) &&
   9                 (0xf == id->model));
  10 }
  11
  12 const struct msrdef intel_core2_early_msrs[] = {
  13         {0x17, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PLATFORM_ID", "", {
  14                 { BITS_EOT }
  15         }},
  16         {0x2a, MSRTYPE_RDWR, MSR2(0, 0), "EBL_CR_POWERON", "", {
  17                 { BITS_EOT }
  18         }},
  19         {0x3f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TEMPERATURE_OFFSET", "", {
  20                 { BITS_EOT }
  21         }},
  22         {0xa8, MSRTYPE_RDWR, MSR2(0, 0), "EMTTM_CR_TABLE0", "", {
  23                 { BITS_EOT }
  24         }},
  25         {0xa9, MSRTYPE_RDWR, MSR2(0, 0), "EMTTM_CR_TABLE1", "", {
  26                 { BITS_EOT }
  27         }},
  28         {0xaa, MSRTYPE_RDWR, MSR2(0, 0), "EMTTM_CR_TABLE2", "", {
  29                 { BITS_EOT }
  30         }},
  31         {0xab, MSRTYPE_RDWR, MSR2(0, 0), "EMTTM_CR_TABLE3", "", {
  32                 { BITS_EOT }
  33         }},
  34         {0xac, MSRTYPE_RDWR, MSR2(0, 0), "EMTTM_CR_TABLE4", "", {
  35                 { BITS_EOT }
  36         }},
  37         {0xad, MSRTYPE_RDWR, MSR2(0, 0), "EMTTM_CR_TABLE5", "", {
  38                 { BITS_EOT }
  39         }},
  40         {0xcd, MSRTYPE_RDWR, MSR2(0, 0), "FSB_CLOCK_STS", "", {
  41                 { BITS_EOT }
  42         }},
  43         {0xe2, MSRTYPE_RDWR, MSR2(0, 0), "PMG_CST_CONFIG_CONTROL", "", {
  44                 { BITS_EOT }
  45         }},
  46         {0xe3, MSRTYPE_RDWR, MSR2(0, 0), "PMG_IO_BASE_ADDR", "", {
  47                 { BITS_EOT }
  48         }},
  49         {0xe4, MSRTYPE_RDWR, MSR2(0, 0), "PMG_IO_CAPTURE_ADDR", "", {
  50                 { BITS_EOT }
  51         }},
  52         {0xee, MSRTYPE_RDWR, MSR2(0, 0), "EXT_CONFIG", "", {
  53                 { BITS_EOT }
  54         }},
  55         {0x11e, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_CTL3", "", {
  56                 { BITS_EOT }
  57         }},
  58         {0x194, MSRTYPE_RDWR, MSR2(0, 0), "CLOCK_FLEX_MAX", "", {
  59                 { BITS_EOT }
  60         }},
  61         {0x198, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_STATUS", "", {
  62                 { BITS_EOT }
  63         }},
  64         {0x1a0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MISC_ENABLES", "", {
  65                 { BITS_EOT }
  66         }},
  67         {0x1aa, MSRTYPE_RDWR, MSR2(0, 0), "PIC_SENS_CFG", "", {
  68                 { BITS_EOT }
  69         }},
  70         {0x400, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_CTL", "", {
  71                 { BITS_EOT }
  72         }},
  73         {0x401, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_STATUS", "", {
  74                 { BITS_EOT }
  75         }},
  76         {0x402, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_ADDR", "", {
  77                 { BITS_EOT }
  78         }},
  79         {0x40c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_CTL", "", {
  80                 { BITS_EOT }
  81         }},
  82         {0x40d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_STATUS", "", {
  83                 { BITS_EOT }
  84         }},
  85         {0x40e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_ADDR", "", {
  86                 { BITS_EOT }
  87         }},
  88         {0x10, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STAMP_COUNTER", "", {
  89                 { BITS_EOT }
  90         }},
  91         {0x1b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APIC_BASE", "", {
  92                 { BITS_EOT }
  93         }},
  94         {0x3a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FEATURE_CONTROL", "", {
  95                 { BITS_EOT }
  96         }},
  97         {0x8b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_SIGN_ID", "", {
  98                 { BITS_EOT }
  99         }},
 100         {0xe1, MSRTYPE_RDWR, MSR2(0, 0), "SMM_CST_MISC_INFO", "", {
 101                 { BITS_EOT }
 102         }},
 103         {0xe7, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MPERF", "", {
 104                 { BITS_EOT }
 105         }},
 106         {0xe8, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APERF", "", {
 107                 { BITS_EOT }
 108         }},
 109         {0xfe, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRRCAP", "", {
 110                 { BITS_EOT }
 111         }},
 112         {0x179, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_CAP", "", {
 113                 { BITS_EOT }
 114         }},
 115         {0x17a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_STATUS", "", {
 116                 { BITS_EOT }
 117         }},
 118         {0x199, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_CONTROL", "", {
 119                 { BITS_EOT }
 120         }},
 121         {0x19a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_CTL", "", {
 122                 { BITS_EOT }
 123         }},
 124         {0x19b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_INTERRUPT", "", {
 125                 { BITS_EOT }
 126         }},
 127         {0x19c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_STATUS", "", {
 128                 { BITS_EOT }
 129         }},
 130         {0x19d, MSRTYPE_RDWR, MSR2(0, 0), "MSR_THERM2_CTL", "", {
 131                 { BITS_EOT }
 132         }},
 133         {0x1d9, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DEBUGCTL", "", {
 134                 { BITS_EOT }
 135         }},
 136         {0x200, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE0", "", {
 137                 { BITS_EOT }
 138         }},
 139         {0x201, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK0", "", {
 140                 { BITS_EOT }
 141         }},
 142         {0x202, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE1", "", {
 143                 { BITS_EOT }
 144         }},
 145         {0x203, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK1", "", {
 146                 { BITS_EOT }
 147         }},
 148         {0x204, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE2", "", {
 149                 { BITS_EOT }
 150         }},
 151         {0x205, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK2", "", {
 152                 { BITS_EOT }
 153         }},
 154         {0x206, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE3", "", {
 155                 { BITS_EOT }
 156         }},
 157         {0x207, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK3", "", {
 158                 { BITS_EOT }
 159         }},
 160         {0x208, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE4", "", {
 161                 { BITS_EOT }
 162         }},
 163         {0x209, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK4", "", {
 164                 { BITS_EOT }
 165         }},
 166         {0x20a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE5", "", {
 167                 { BITS_EOT }
 168         }},
 169         {0x20b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK5", "", {
 170                 { BITS_EOT }
 171         }},
 172         {0x20c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE6", "", {
 173                 { BITS_EOT }
 174         }},
 175         {0x20d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK6", "", {
 176                 { BITS_EOT }
 177         }},
 178         {0x20e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE7", "", {
 179                 { BITS_EOT }
 180         }},
 181         {0x20f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK7", "", {
 182                 { BITS_EOT }
 183         }},
 184         {0x250, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX64K_00000", "", {
 185                 { BITS_EOT }
 186         }},
 187         {0x258, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_80000", "", {
 188                 { BITS_EOT }
 189         }},
 190         {0x259, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_A0000", "", {
 191                 { BITS_EOT }
 192         }},
 193         {0x268, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C0000", "", {
 194                 { BITS_EOT }
 195         }},
 196         {0x269, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C8000", "", {
 197                 { BITS_EOT }
 198         }},
 199         {0x26a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D0000", "", {
 200                 { BITS_EOT }
 201         }},
 202         {0x26b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D8000", "", {
 203                 { BITS_EOT }
 204         }},
 205         {0x26c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E0000", "", {
 206                 { BITS_EOT }
 207         }},
 208         {0x26d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E8000", "", {
 209                 { BITS_EOT }
 210         }},
 211         {0x26e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F0000", "", {
 212                 { BITS_EOT }
 213         }},
 214         {0x26f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F8000", "", {
 215                 { BITS_EOT }
 216         }},
 217         {0x2ff, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_DEF_TYPE", "", {
 218                 { BITS_EOT }
 219         }},
 220         { MSR_EOT }
 221 };