src/southbridge/intel/ibexpeak/early_thermal.c

   1 /* This file is part of the coreboot project. */
   2 /* SPDX-License-Identifier: GPL-2.0-or-later */
   3
   4 #include <device/mmio.h>
   5 #include <device/pci_ops.h>
   6 #include "pch.h"
   7 #include "cpu/intel/model_2065x/model_2065x.h"
   8 #include <cpu/x86/msr.h>
   9
  10 /* Early thermal init, must be done prior to giving ME its memory
  11    which is done at the end of raminit.  */
  12 void early_thermal_init(void)
  13 {
  14         pci_devfn_t dev;
  15         msr_t msr;
  16
  17         dev = PCI_DEV(0x0, 0x1f, 0x6);
  18
  19         /* Program address for temporary BAR.  */
  20         pci_write_config32(dev, 0x40, 0x40000000);
  21         pci_write_config32(dev, 0x44, 0x0);
  22
  23         /* Activate temporary BAR.  */
  24         pci_write_config32(dev, 0x40,
  25                            pci_read_config32(dev, 0x40) | 5);
  26
  27         /* Perform init.  */
  28         /* Configure TJmax.  */
  29         msr = rdmsr(MSR_TEMPERATURE_TARGET);
  30         write16((u16 *)0x40000012, ((msr.lo >> 16) & 0xff) << 6);
  31         /* Northbridge temperature slope and offset.  */
  32         write16((u16 *)0x40000016, 0x7746);
  33         /* Enable thermal data reporting, processor, PCH and northbridge.  */
  34         write16((u16 *)0x4000001a,
  35                 (read16((u16 *)0x4000001a) & ~0xf) | 0x10f0);
  36
  37         /* Disable temporary BAR.  */
  38         pci_write_config32(dev, 0x40,
  39                            pci_read_config32(dev, 0x40) & ~1);
  40         pci_write_config32(dev, 0x40, 0);
  41 }