src/southbridge/intel/i82371eb/early_pm.c

   1 /* This file is part of the coreboot project. */
   2 /* SPDX-License-Identifier: GPL-2.0-or-later */
   3
   4 #include <stdint.h>
   5 #include <device/pci_ops.h>
   6 #include <device/pci.h>
   7 #include <device/pci_def.h>
   8 #include <device/pci_ids.h>
   9 #include "i82371eb.h"
  10
  11 void enable_pm(void)
  12 {
  13         pci_devfn_t dev;
  14         u8 reg8;
  15         u16 reg16;
  16
  17         /* Get the SMBus/PM device of the 82371AB/EB/MB. */
  18         dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
  19                                 PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
  20
  21         /* Set the PM I/O base. */
  22         pci_write_config32(dev, PMBA, DEFAULT_PMBASE | 1);
  23
  24         /* Enable access to the PM I/O space. */
  25         reg16 = pci_read_config16(dev, PCI_COMMAND);
  26         reg16 |= PCI_COMMAND_IO;
  27         pci_write_config16(dev, PCI_COMMAND, reg16);
  28
  29         /* PM I/O Space Enable (PMIOSE). */
  30         reg8 = pci_read_config8(dev, PMREGMISC);
  31         reg8 |= PMIOSE;
  32         pci_write_config8(dev, PMREGMISC, reg8);
  33 }