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treewide: replace GPLv2 long form headers with SPDX header
[coreboot.git] / src / southbridge / intel / common / spi.c
blob380940c73932aff5727cc1a60433bc9e9ad3a54e
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #define __SIMPLE_DEVICE__
4
5 /* This file is derived from the flashrom project. */
6
7 #include <stdint.h>
8 #include <string.h>
9 #include <bootstate.h>
10 #include <commonlib/helpers.h>
11 #include <delay.h>
12 #include <device/mmio.h>
13 #include <device/pci_ops.h>
14 #include <console/console.h>
15 #include <device/device.h>
16 #include <device/pci.h>
17 #include <spi_flash.h>
18 #include <spi-generic.h>
19 #include <timer.h>
20
21 #include "spi.h"
22
23 #define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
24 #define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
25 #define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
26 #define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
27
28 static int spi_is_multichip(void);
29
30 struct ich7_spi_regs {
31 uint16_t spis;
32 uint16_t spic;
33 uint32_t spia;
34 uint64_t spid[8];
35 uint64_t _pad;
36 uint32_t bbar;
37 uint16_t preop;
38 uint16_t optype;
39 uint8_t opmenu[8];
40 uint32_t pbr[3];
41 } __packed;
42
43 struct ich9_spi_regs {
44 uint32_t bfpr;
45 uint16_t hsfs;
46 uint16_t hsfc;
47 uint32_t faddr;
48 uint32_t _reserved0;
49 uint32_t fdata[16];
50 uint32_t frap;
51 uint32_t freg[5];
52 uint32_t _reserved1[3];
53 uint32_t pr[5];
54 uint32_t _reserved2[2];
55 uint8_t ssfs;
56 uint8_t ssfc[3];
57 uint16_t preop;
58 uint16_t optype;
59 uint8_t opmenu[8];
60 uint32_t bbar;
61 uint8_t _reserved3[12];
62 uint32_t fdoc;
63 uint32_t fdod;
64 uint8_t _reserved4[8];
65 uint32_t afc;
66 uint32_t lvscc;
67 uint32_t uvscc;
68 uint8_t _reserved5[4];
69 uint32_t fpb;
70 uint8_t _reserved6[28];
71 uint32_t srdl;
72 uint32_t srdc;
73 uint32_t srd;
74 } __packed;
75
76 struct ich_spi_controller {
77 int locked;
78 uint32_t flmap0;
79 uint32_t flcomp;
80 uint32_t hsfs;
81
82 union {
83 struct ich9_spi_regs *ich9_spi;
84 struct ich7_spi_regs *ich7_spi;
85 };
86 uint8_t *opmenu;
87 int menubytes;
88 uint16_t *preop;
89 uint16_t *optype;
90 uint32_t *addr;
91 uint8_t *data;
92 unsigned int databytes;
93 uint8_t *status;
94 uint16_t *control;
95 uint32_t *bbar;
96 uint32_t *fpr;
97 uint8_t fpr_max;
98 };
99
100 static struct ich_spi_controller cntlr;
101
102 enum {
103 SPIS_SCIP = 0x0001,
104 SPIS_GRANT = 0x0002,
105 SPIS_CDS = 0x0004,
106 SPIS_FCERR = 0x0008,
107 SSFS_AEL = 0x0010,
108 SPIS_LOCK = 0x8000,
109 SPIS_RESERVED_MASK = 0x7ff0,
110 SSFS_RESERVED_MASK = 0x7fe2
111 };
112
113 enum {
114 SPIC_SCGO = 0x000002,
115 SPIC_ACS = 0x000004,
116 SPIC_SPOP = 0x000008,
117 SPIC_DBC = 0x003f00,
118 SPIC_DS = 0x004000,
119 SPIC_SME = 0x008000,
120 SSFC_SCF_MASK = 0x070000,
121 SSFC_RESERVED = 0xf80000
122 };
123
124 enum {
125 HSFS_FDONE = 0x0001,
126 HSFS_FCERR = 0x0002,
127 HSFS_AEL = 0x0004,
128 HSFS_BERASE_MASK = 0x0018,
129 HSFS_BERASE_SHIFT = 3,
130 HSFS_SCIP = 0x0020,
131 HSFS_FDOPSS = 0x2000,
132 HSFS_FDV = 0x4000,
133 HSFS_FLOCKDN = 0x8000
134 };
135
136 enum {
137 HSFC_FGO = 0x0001,
138 HSFC_FCYCLE_MASK = 0x0006,
139 HSFC_FCYCLE_SHIFT = 1,
140 HSFC_FDBC_MASK = 0x3f00,
141 HSFC_FDBC_SHIFT = 8,
142 HSFC_FSMIE = 0x8000
143 };
144
145 enum {
146 SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0,
147 SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1,
148 SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2,
149 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3
150 };
151
152 #if CONFIG(DEBUG_SPI_FLASH)
153
154 static u8 readb_(const void *addr)
155 {
156 u8 v = read8(addr);
157
158 printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
159 v, ((unsigned int) addr & 0xffff) - 0xf020);
160 return v;
161 }
162
163 static u16 readw_(const void *addr)
164 {
165 u16 v = read16(addr);
166
167 printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
168 v, ((unsigned int) addr & 0xffff) - 0xf020);
169 return v;
170 }
171
172 static u32 readl_(const void *addr)
173 {
174 u32 v = read32(addr);
175
176 printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
177 v, ((unsigned int) addr & 0xffff) - 0xf020);
178 return v;
179 }
180
181 static void writeb_(u8 b, void *addr)
182 {
183 write8(addr, b);
184 printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
185 b, ((unsigned int) addr & 0xffff) - 0xf020);
186 }
187
188 static void writew_(u16 b, void *addr)
189 {
190 write16(addr, b);
191 printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
192 b, ((unsigned int) addr & 0xffff) - 0xf020);
193 }
194
195 static void writel_(u32 b, void *addr)
196 {
197 write32(addr, b);
198 printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
199 b, ((unsigned int) addr & 0xffff) - 0xf020);
200 }
201
202 #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
203
204 #define readb_(a) read8(a)
205 #define readw_(a) read16(a)
206 #define readl_(a) read32(a)
207 #define writeb_(val, addr) write8(addr, val)
208 #define writew_(val, addr) write16(addr, val)
209 #define writel_(val, addr) write32(addr, val)
210
211 #endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
212
213 static void write_reg(const void *value, void *dest, uint32_t size)
214 {
215 const uint8_t *bvalue = value;
216 uint8_t *bdest = dest;
217
218 while (size >= 4) {
219 writel_(*(const uint32_t *)bvalue, bdest);
220 bdest += 4; bvalue += 4; size -= 4;
221 }
222 while (size) {
223 writeb_(*bvalue, bdest);
224 bdest++; bvalue++; size--;
225 }
226 }
227
228 static void read_reg(const void *src, void *value, uint32_t size)
229 {
230 const uint8_t *bsrc = src;
231 uint8_t *bvalue = value;
232
233 while (size >= 4) {
234 *(uint32_t *)bvalue = readl_(bsrc);
235 bsrc += 4; bvalue += 4; size -= 4;
236 }
237 while (size) {
238 *bvalue = readb_(bsrc);
239 bsrc++; bvalue++; size--;
240 }
241 }
242
243 static void ich_set_bbar(uint32_t minaddr)
244 {
245 const uint32_t bbar_mask = 0x00ffff00;
246 uint32_t ichspi_bbar;
247
248 minaddr &= bbar_mask;
249 ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask;
250 ichspi_bbar |= minaddr;
251 writel_(ichspi_bbar, cntlr.bbar);
252 }
253
254 #if CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
255 #define MENU_BYTES member_size(struct ich7_spi_regs, opmenu)
256 #else
257 #define MENU_BYTES member_size(struct ich9_spi_regs, opmenu)
258 #endif
259
260 #define RCBA 0xf0
261 #define SBASE 0x54
262
263 static void *get_spi_bar(pci_devfn_t dev)
264 {
265 uintptr_t rcba; /* Root Complex Register Block */
266 uintptr_t sbase;
267
268 if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) {
269 rcba = pci_read_config32(dev, RCBA);
270 return (void *)((rcba & 0xffffc000) + 0x3020);
271 }
272 if (CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT)) {
273 sbase = pci_read_config32(dev, SBASE);
274 sbase &= ~0x1ff;
275 return (void *)sbase;
276 }
277 if (CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9)) {
278 rcba = pci_read_config32(dev, RCBA);
279 return (void *)((rcba & 0xffffc000) + 0x3800);
280 }
281 }
282
283 void spi_init(void)
284 {
285 uint8_t bios_cntl;
286 struct ich9_spi_regs *ich9_spi;
287 struct ich7_spi_regs *ich7_spi;
288 uint16_t hsfs;
289
290 pci_devfn_t dev = PCI_DEV(0, 31, 0);
291
292 if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) {
293 ich7_spi = get_spi_bar(dev);
294 cntlr.ich7_spi = ich7_spi;
295 cntlr.opmenu = ich7_spi->opmenu;
296 cntlr.menubytes = sizeof(ich7_spi->opmenu);
297 cntlr.optype = &ich7_spi->optype;
298 cntlr.addr = &ich7_spi->spia;
299 cntlr.data = (uint8_t *)ich7_spi->spid;
300 cntlr.databytes = sizeof(ich7_spi->spid);
301 cntlr.status = (uint8_t *)&ich7_spi->spis;
302 cntlr.control = &ich7_spi->spic;
303 cntlr.bbar = &ich7_spi->bbar;
304 cntlr.preop = &ich7_spi->preop;
305 cntlr.fpr = &ich7_spi->pbr[0];
306 cntlr.fpr_max = 3;
307 } else {
308 ich9_spi = get_spi_bar(dev);
309 cntlr.ich9_spi = ich9_spi;
310 hsfs = readw_(&ich9_spi->hsfs);
311 cntlr.hsfs = hsfs;
312 cntlr.opmenu = ich9_spi->opmenu;
313 cntlr.menubytes = sizeof(ich9_spi->opmenu);
314 cntlr.optype = &ich9_spi->optype;
315 cntlr.addr = &ich9_spi->faddr;
316 cntlr.data = (uint8_t *)ich9_spi->fdata;
317 cntlr.databytes = sizeof(ich9_spi->fdata);
318 cntlr.status = &ich9_spi->ssfs;
319 cntlr.control = (uint16_t *)ich9_spi->ssfc;
320 cntlr.bbar = &ich9_spi->bbar;
321 cntlr.preop = &ich9_spi->preop;
322 cntlr.fpr = &ich9_spi->pr[0];
323 cntlr.fpr_max = 5;
324
325 if (cntlr.hsfs & HSFS_FDV) {
326 writel_(4, &ich9_spi->fdoc);
327 cntlr.flmap0 = readl_(&ich9_spi->fdod);
328 writel_(0x1000, &ich9_spi->fdoc);
329 cntlr.flcomp = readl_(&ich9_spi->fdod);
330 }
331 }
332
333 ich_set_bbar(0);
334
335 if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX) || CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9)) {
336 /* Disable the BIOS write protect so write commands are allowed. */
337 bios_cntl = pci_read_config8(dev, 0xdc);
338 /* Deassert SMM BIOS Write Protect Disable. */
339 bios_cntl &= ~(1 << 5);
340 pci_write_config8(dev, 0xdc, bios_cntl | 0x1);
341 }
342 }
343
344 static int spi_locked(void)
345 {
346 if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) {
347 return !!(readw_(&cntlr.ich7_spi->spis) & HSFS_FLOCKDN);
348 } else {
349 return !!(readw_(&cntlr.ich9_spi->hsfs) & HSFS_FLOCKDN);
350 }
351 }
352
353 static void spi_init_cb(void *unused)
354 {
355 spi_init();
356 }
357
358 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
359
360 typedef struct spi_transaction {
361 const uint8_t *out;
362 uint32_t bytesout;
363 uint8_t *in;
364 uint32_t bytesin;
365 uint8_t type;
366 uint8_t opcode;
367 uint32_t offset;
368 } spi_transaction;
369
370 static inline void spi_use_out(spi_transaction *trans, unsigned int bytes)
371 {
372 trans->out += bytes;
373 trans->bytesout -= bytes;
374 }
375
376 static inline void spi_use_in(spi_transaction *trans, unsigned int bytes)
377 {
378 trans->in += bytes;
379 trans->bytesin -= bytes;
380 }
381
382 static void spi_setup_type(spi_transaction *trans)
383 {
384 trans->type = 0xFF;
385
386 /* Try to guess spi type from read/write sizes. */
387 if (trans->bytesin == 0) {
388 if (trans->bytesout > 4)
389 /*
390 * If bytesin = 0 and bytesout > 4, we presume this is
391 * a write data operation, which is accompanied by an
392 * address.
393 */
394 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
395 else
396 trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
397 return;
398 }
399
400 if (trans->bytesout == 1) { /* and bytesin is > 0 */
401 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
402 return;
403 }
404
405 if (trans->bytesout == 4) { /* and bytesin is > 0 */
406 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
407 }
408
409 /* Fast read command is called with 5 bytes instead of 4 */
410 if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
411 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
412 --trans->bytesout;
413 }
414 }
415
416 static int spi_setup_opcode(spi_transaction *trans)
417 {
418 uint16_t optypes;
419 uint8_t opmenu[MENU_BYTES];
420
421 trans->opcode = trans->out[0];
422 spi_use_out(trans, 1);
423 if (!spi_locked()) {
424 /* The lock is off, so just use index 0. */
425 writeb_(trans->opcode, cntlr.opmenu);
426 optypes = readw_(cntlr.optype);
427 optypes = (optypes & 0xfffc) | (trans->type & 0x3);
428 writew_(optypes, cntlr.optype);
429 return 0;
430 }
431
432 /* The lock is on. See if what we need is on the menu. */
433 uint8_t optype;
434 uint16_t opcode_index;
435
436 /* Write Enable is handled as atomic prefix */
437 if (trans->opcode == SPI_OPCODE_WREN)
438 return 0;
439
440 read_reg(cntlr.opmenu, opmenu, sizeof(opmenu));
441 for (opcode_index = 0; opcode_index < ARRAY_SIZE(opmenu); opcode_index++) {
442 if (opmenu[opcode_index] == trans->opcode)
443 break;
444 }
445
446 if (opcode_index == ARRAY_SIZE(opmenu)) {
447 printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n",
448 trans->opcode);
449 return -1;
450 }
451
452 optypes = readw_(cntlr.optype);
453 optype = (optypes >> (opcode_index * 2)) & 0x3;
454 if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
455 optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
456 trans->bytesout >= 3) {
457 /* We guessed wrong earlier. Fix it up. */
458 trans->type = optype;
459 }
460 if (optype != trans->type) {
461 printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n",
462 optype);
463 return -1;
464 }
465 return opcode_index;
466 }
467
468 static int spi_setup_offset(spi_transaction *trans)
469 {
470 /* Separate the SPI address and data. */
471 switch (trans->type) {
472 case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
473 case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
474 return 0;
475 case SPI_OPCODE_TYPE_READ_WITH_ADDRESS:
476 case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS:
477 trans->offset = ((uint32_t)trans->out[0] << 16) |
478 ((uint32_t)trans->out[1] << 8) |
479 ((uint32_t)trans->out[2] << 0);
480 spi_use_out(trans, 3);
481 return 1;
482 default:
483 printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type);
484 return -1;
485 }
486 }
487
488 /*
489 * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
490 * below is True) or 0. In case the wait was for the bit(s) to set - write
491 * those bits back, which would cause resetting them.
492 *
493 * Return the last read status value on success or -1 on failure.
494 */
495 static int ich_status_poll(u16 bitmask, int wait_til_set)
496 {
497 int timeout = 600000; /* This will result in 6 seconds */
498 u16 status = 0;
499
500 while (timeout--) {
501 status = readw_(cntlr.status);
502 if (wait_til_set ^ ((status & bitmask) == 0)) {
503 if (wait_til_set)
504 writew_((status & bitmask), cntlr.status);
505 return status;
506 }
507 udelay(10);
508 }
509
510 printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, bitmask %x\n",
511 status, bitmask);
512 return -1;
513 }
514
515 static int spi_is_multichip(void)
516 {
517 if (!(cntlr.hsfs & HSFS_FDV))
518 return 0;
519 return !!((cntlr.flmap0 >> 8) & 3);
520 }
521
522 static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
523 size_t bytesout, void *din, size_t bytesin)
524 {
525 uint16_t control;
526 int16_t opcode_index;
527 int with_address;
528 int status;
529
530 spi_transaction trans = {
531 dout, bytesout,
532 din, bytesin,
533 0xff, 0xff, 0
534 };
535
536 /* There has to always at least be an opcode. */
537 if (!bytesout || !dout) {
538 printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n");
539 return -1;
540 }
541 /* Make sure if we read something we have a place to put it. */
542 if (bytesin != 0 && !din) {
543 printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n");
544 return -1;
545 }
546
547 if (ich_status_poll(SPIS_SCIP, 0) == -1)
548 return -1;
549
550 writew_(SPIS_CDS | SPIS_FCERR, cntlr.status);
551
552 spi_setup_type(&trans);
553 if ((opcode_index = spi_setup_opcode(&trans)) < 0)
554 return -1;
555 if ((with_address = spi_setup_offset(&trans)) < 0)
556 return -1;
557
558 if (trans.opcode == SPI_OPCODE_WREN) {
559 /*
560 * Treat Write Enable as Atomic Pre-Op if possible
561 * in order to prevent the Management Engine from
562 * issuing a transaction between WREN and DATA.
563 */
564 if (!spi_locked())
565 writew_(trans.opcode, cntlr.preop);
566 return 0;
567 }
568
569 /* Preset control fields */
570 control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
571
572 /* Issue atomic preop cycle if needed */
573 if (readw_(cntlr.preop))
574 control |= SPIC_ACS;
575
576 if (!trans.bytesout && !trans.bytesin) {
577 /* SPI addresses are 24 bit only */
578 if (with_address)
579 writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
580
581 /*
582 * This is a 'no data' command (like Write Enable), its
583 * bitesout size was 1, decremented to zero while executing
584 * spi_setup_opcode() above. Tell the chip to send the
585 * command.
586 */
587 writew_(control, cntlr.control);
588
589 /* wait for the result */
590 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
591 if (status == -1)
592 return -1;
593
594 if (status & SPIS_FCERR) {
595 printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n");
596 return -1;
597 }
598
599 goto spi_xfer_exit;
600 }
601
602 /*
603 * Check if this is a write command attempting to transfer more bytes
604 * than the controller can handle. Iterations for writes are not
605 * supported here because each SPI write command needs to be preceded
606 * and followed by other SPI commands, and this sequence is controlled
607 * by the SPI chip driver.
608 */
609 if (trans.bytesout > cntlr.databytes) {
610 printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use"
611 " spi_crop_chunk()?\n");
612 return -1;
613 }
614
615 /*
616 * Read or write up to databytes bytes at a time until everything has
617 * been sent.
618 */
619 while (trans.bytesout || trans.bytesin) {
620 uint32_t data_length;
621
622 /* SPI addresses are 24 bit only */
623 writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
624
625 if (trans.bytesout)
626 data_length = MIN(trans.bytesout, cntlr.databytes);
627 else
628 data_length = MIN(trans.bytesin, cntlr.databytes);
629
630 /* Program data into FDATA0 to N */
631 if (trans.bytesout) {
632 write_reg(trans.out, cntlr.data, data_length);
633 spi_use_out(&trans, data_length);
634 if (with_address)
635 trans.offset += data_length;
636 }
637
638 /* Add proper control fields' values */
639 control &= ~((cntlr.databytes - 1) << 8);
640 control |= SPIC_DS;
641 control |= (data_length - 1) << 8;
642
643 /* write it */
644 writew_(control, cntlr.control);
645
646 /* Wait for Cycle Done Status or Flash Cycle Error. */
647 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
648 if (status == -1)
649 return -1;
650
651 if (status & SPIS_FCERR) {
652 printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n");
653 return -1;
654 }
655
656 if (trans.bytesin) {
657 read_reg(cntlr.data, trans.in, data_length);
658 spi_use_in(&trans, data_length);
659 if (with_address)
660 trans.offset += data_length;
661 }
662 }
663
664 spi_xfer_exit:
665 /* Clear atomic preop now that xfer is done */
666 writew_(0, cntlr.preop);
667
668 return 0;
669 }
670
671 /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */
672 static void ich_hwseq_set_addr(uint32_t addr)
673 {
674 uint32_t addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF;
675
676 writel_((addr & 0x01FFFFFF) | addr_old, &cntlr.ich9_spi->faddr);
677 }
678
679 /* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
680 Resets all error flags in HSFS.
681 Returns 0 if the cycle completes successfully without errors within
682 timeout us, 1 on errors. */
683 static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
684 unsigned int len)
685 {
686 uint16_t hsfs;
687 uint32_t addr;
688
689 timeout /= 8; /* scale timeout duration to counter */
690 while ((((hsfs = readw_(&cntlr.ich9_spi->hsfs)) &
691 (HSFS_FDONE | HSFS_FCERR)) == 0) &&
692 --timeout) {
693 udelay(8);
694 }
695 writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
696
697 if (!timeout) {
698 uint16_t hsfc;
699 addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF;
700 hsfc = readw_(&cntlr.ich9_spi->hsfc);
701 printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and "
702 "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n",
703 addr, addr + len - 1, addr, len - 1,
704 hsfc, hsfs);
705 return 1;
706 }
707
708 if (hsfs & HSFS_FCERR) {
709 uint16_t hsfc;
710 addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF;
711 hsfc = readw_(&cntlr.ich9_spi->hsfc);
712 printk(BIOS_ERR, "Transaction error between offset 0x%08x and "
713 "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n",
714 addr, addr + len - 1, addr, len - 1,
715 hsfc, hsfs);
716 return 1;
717 }
718 return 0;
719 }
720
721
722 static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset,
723 size_t len)
724 {
725 u32 start, end, erase_size;
726 int ret;
727 uint16_t hsfc;
728 unsigned int timeout = 1000 * USECS_PER_MSEC; /* 1 second timeout */
729
730 erase_size = flash->sector_size;
731 if (offset % erase_size || len % erase_size) {
732 printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n");
733 return -1;
734 }
735
736 ret = spi_claim_bus(&flash->spi);
737 if (ret) {
738 printk(BIOS_ERR, "SF: Unable to claim SPI bus\n");
739 return ret;
740 }
741
742 start = offset;
743 end = start + len;
744
745 while (offset < end) {
746 /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
747 writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
748
749 ich_hwseq_set_addr(offset);
750
751 offset += erase_size;
752
753 hsfc = readw_(&cntlr.ich9_spi->hsfc);
754 hsfc &= ~HSFC_FCYCLE; /* clear operation */
755 hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */
756 hsfc |= HSFC_FGO; /* start */
757 writew_(hsfc, &cntlr.ich9_spi->hsfc);
758 if (ich_hwseq_wait_for_cycle_complete(timeout, len)) {
759 printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size);
760 ret = -1;
761 goto out;
762 }
763 }
764
765 printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start);
766
767 out:
768 spi_release_bus(&flash->spi);
769 return ret;
770 }
771
772 static void ich_read_data(uint8_t *data, int len)
773 {
774 int i;
775 uint32_t temp32 = 0;
776
777 for (i = 0; i < len; i++) {
778 if ((i % 4) == 0)
779 temp32 = readl_(cntlr.data + i);
780
781 data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
782 }
783 }
784
785 static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len,
786 void *buf)
787 {
788 uint16_t hsfc;
789 uint16_t timeout = 100 * 60;
790 uint8_t block_len;
791
792 if (addr + len > flash->size) {
793 printk(BIOS_ERR,
794 "Attempt to read %x-%x which is out of chip\n",
795 (unsigned int) addr,
796 (unsigned int) addr+(unsigned int) len);
797 return -1;
798 }
799
800 /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
801 writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
802
803 while (len > 0) {
804 block_len = MIN(len, cntlr.databytes);
805 if (block_len > (~addr & 0xff))
806 block_len = (~addr & 0xff) + 1;
807 ich_hwseq_set_addr(addr);
808 hsfc = readw_(&cntlr.ich9_spi->hsfc);
809 hsfc &= ~HSFC_FCYCLE; /* set read operation */
810 hsfc &= ~HSFC_FDBC; /* clear byte count */
811 /* set byte count */
812 hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
813 hsfc |= HSFC_FGO; /* start */
814 writew_(hsfc, &cntlr.ich9_spi->hsfc);
815
816 if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
817 return 1;
818 ich_read_data(buf, block_len);
819 addr += block_len;
820 buf += block_len;
821 len -= block_len;
822 }
823 return 0;
824 }
825
826 /* Fill len bytes from the data array into the fdata/spid registers.
827 *
828 * Note that using len > flash->pgm->spi.max_data_write will trash the registers
829 * following the data registers.
830 */
831 static void ich_fill_data(const uint8_t *data, int len)
832 {
833 uint32_t temp32 = 0;
834 int i;
835
836 if (len <= 0)
837 return;
838
839 for (i = 0; i < len; i++) {
840 if ((i % 4) == 0)
841 temp32 = 0;
842
843 temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
844
845 if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
846 writel_(temp32, cntlr.data + (i - (i % 4)));
847 }
848 i--;
849 if ((i % 4) != 3) /* Write remaining data to regs. */
850 writel_(temp32, cntlr.data + (i - (i % 4)));
851 }
852
853 static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
854 const void *buf)
855 {
856 uint16_t hsfc;
857 uint16_t timeout = 100 * 60;
858 uint8_t block_len;
859 uint32_t start = addr;
860
861 if (addr + len > flash->size) {
862 printk(BIOS_ERR,
863 "Attempt to write 0x%x-0x%x which is out of chip\n",
864 (unsigned int)addr, (unsigned int) (addr+len));
865 return -1;
866 }
867
868 /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
869 writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
870
871 while (len > 0) {
872 block_len = MIN(len, cntlr.databytes);
873 if (block_len > (~addr & 0xff))
874 block_len = (~addr & 0xff) + 1;
875
876 ich_hwseq_set_addr(addr);
877
878 ich_fill_data(buf, block_len);
879 hsfc = readw_(&cntlr.ich9_spi->hsfc);
880 hsfc &= ~HSFC_FCYCLE; /* clear operation */
881 hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */
882 hsfc &= ~HSFC_FDBC; /* clear byte count */
883 /* set byte count */
884 hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
885 hsfc |= HSFC_FGO; /* start */
886 writew_(hsfc, &cntlr.ich9_spi->hsfc);
887
888 if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) {
889 printk(BIOS_ERR, "SF: write failure at %x\n",
890 addr);
891 return -1;
892 }
893 addr += block_len;
894 buf += block_len;
895 len -= block_len;
896 }
897 printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n",
898 (unsigned int) (addr - start), start);
899 return 0;
900 }
901
902 static const struct spi_flash_ops spi_flash_ops = {
903 .read = ich_hwseq_read,
904 .write = ich_hwseq_write,
905 .erase = ich_hwseq_erase,
906 };
907
908 static int spi_flash_programmer_probe(const struct spi_slave *spi,
909 struct spi_flash *flash)
910 {
911
912 if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX))
913 return spi_flash_generic_probe(spi, flash);
914
915 /* Try generic probing first if spi_is_multichip returns 0. */
916 if (!spi_is_multichip() && !spi_flash_generic_probe(spi, flash))
917 return 0;
918
919 memcpy(&flash->spi, spi, sizeof(*spi));
920
921 ich_hwseq_set_addr(0);
922 switch ((cntlr.hsfs >> 3) & 3) {
923 case 0:
924 flash->sector_size = 256;
925 break;
926 case 1:
927 flash->sector_size = 4096;
928 break;
929 case 2:
930 flash->sector_size = 8192;
931 break;
932 case 3:
933 flash->sector_size = 65536;
934 break;
935 }
936
937 flash->size = 1 << (19 + (cntlr.flcomp & 7));
938
939 flash->ops = &spi_flash_ops;
940
941 if ((cntlr.hsfs & HSFS_FDV) && ((cntlr.flmap0 >> 8) & 3))
942 flash->size += 1 << (19 + ((cntlr.flcomp >> 3) & 7));
943 printk(BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size);
944
945 return 0;
946 }
947
948 static int xfer_vectors(const struct spi_slave *slave,
949 struct spi_op vectors[], size_t count)
950 {
951 return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer);
952 }
953
954 #define SPI_FPR_SHIFT 12
955 #define ICH7_SPI_FPR_MASK 0xfff
956 #define ICH9_SPI_FPR_MASK 0x1fff
957 #define SPI_FPR_BASE_SHIFT 0
958 #define ICH7_SPI_FPR_LIMIT_SHIFT 12
959 #define ICH9_SPI_FPR_LIMIT_SHIFT 16
960 #define ICH9_SPI_FPR_RPE (1 << 15) /* Read Protect */
961 #define SPI_FPR_WPE (1 << 31) /* Write Protect */
962
963 static u32 spi_fpr(u32 base, u32 limit)
964 {
965 u32 ret;
966 u32 mask, limit_shift;
967
968 if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) {
969 mask = ICH7_SPI_FPR_MASK;
970 limit_shift = ICH7_SPI_FPR_LIMIT_SHIFT;
971 } else {
972 mask = ICH9_SPI_FPR_MASK;
973 limit_shift = ICH9_SPI_FPR_LIMIT_SHIFT;
974 }
975 ret = ((limit >> SPI_FPR_SHIFT) & mask) << limit_shift;
976 ret |= ((base >> SPI_FPR_SHIFT) & mask) << SPI_FPR_BASE_SHIFT;
977 return ret;
978 }
979
980 /*
981 * Protect range of SPI flash defined by [start, start+size-1] using Flash
982 * Protected Range (FPR) register if available.
983 * Returns 0 on success, -1 on failure of programming fpr registers.
984 */
985 static int spi_flash_protect(const struct spi_flash *flash,
986 const struct region *region,
987 const enum ctrlr_prot_type type)
988 {
989 u32 start = region_offset(region);
990 u32 end = start + region_sz(region) - 1;
991 u32 reg;
992 u32 protect_mask = 0;
993 int fpr;
994 uint32_t *fpr_base;
995
996 fpr_base = cntlr.fpr;
997
998 /* Find first empty FPR */
999 for (fpr = 0; fpr < cntlr.fpr_max; fpr++) {
1000 reg = read32(&fpr_base[fpr]);
1001 if (reg == 0)
1002 break;
1003 }
1004
1005 if (fpr == cntlr.fpr_max) {
1006 printk(BIOS_ERR, "ERROR: No SPI FPR free!\n");
1007 return -1;
1008 }
1009
1010 switch (type) {
1011 case WRITE_PROTECT:
1012 protect_mask |= SPI_FPR_WPE;
1013 break;
1014 case READ_PROTECT:
1015 if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX))
1016 return -1;
1017 protect_mask |= ICH9_SPI_FPR_RPE;
1018 break;
1019 case READ_WRITE_PROTECT:
1020 if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX))
1021 return -1;
1022 protect_mask |= (ICH9_SPI_FPR_RPE | SPI_FPR_WPE);
1023 break;
1024 default:
1025 printk(BIOS_ERR, "ERROR: Seeking invalid protection!\n");
1026 return -1;
1027 }
1028
1029 /* Set protected range base and limit */
1030 reg = spi_fpr(start, end) | protect_mask;
1031
1032 /* Set the FPR register and verify it is protected */
1033 write32(&fpr_base[fpr], reg);
1034 if (reg != read32(&fpr_base[fpr])) {
1035 printk(BIOS_ERR, "ERROR: Unable to set SPI FPR %d\n", fpr);
1036 return -1;
1037 }
1038
1039 printk(BIOS_INFO, "%s: FPR %d is enabled for range 0x%08x-0x%08x\n",
1040 __func__, fpr, start, end);
1041 return 0;
1042 }
1043
1044 void spi_finalize_ops(void)
1045 {
1046 u16 spi_opprefix;
1047 u16 optype = 0;
1048 struct intel_swseq_spi_config spi_config_default = {
1049 {0x06, 0x50}, /* OPPREFIXES: EWSR and WREN */
1050 { /* OPCODE and OPTYPE */
1051 {0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */
1052 {0x02, WRITE_WITH_ADDR}, /* BYPR: Byte Program */
1053 {0x03, READ_WITH_ADDR}, /* READ: Read Data */
1054 {0x05, READ_NO_ADDR}, /* RDSR: Read Status Register */
1055 {0x20, WRITE_WITH_ADDR}, /* SE20: Sector Erase 0x20 */
1056 {0x9f, READ_NO_ADDR}, /* RDID: Read ID */
1057 {0xd8, WRITE_WITH_ADDR}, /* BED8: Block Erase 0xd8 */
1058 {0x0b, READ_WITH_ADDR}, /* FAST: Fast Read */
1059 }
1060 };
1061 struct intel_swseq_spi_config spi_config_aai_write = {
1062 {0x06, 0x50}, /* OPPREFIXES: EWSR and WREN */
1063 { /* OPCODE and OPTYPE */
1064 {0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */
1065 {0x02, WRITE_WITH_ADDR}, /* BYPR: Byte Program */
1066 {0x03, READ_WITH_ADDR}, /* READ: Read Data */
1067 {0x05, READ_NO_ADDR}, /* RDSR: Read Status Register */
1068 {0x20, WRITE_WITH_ADDR}, /* SE20: Sector Erase 0x20 */
1069 {0x9f, READ_NO_ADDR}, /* RDID: Read ID */
1070 {0xad, WRITE_NO_ADDR}, /* Auto Address Increment Word Program */
1071 {0x04, WRITE_NO_ADDR} /* Write Disable */
1072 }
1073 };
1074 const struct spi_flash *flash = boot_device_spi_flash();
1075 struct intel_swseq_spi_config *spi_config = &spi_config_default;
1076 int i;
1077
1078 /*
1079 * Some older SST SPI flashes support AAI write but use 0xaf opcde for
1080 * that. Flashrom uses the byte program opcode to write those flashes,
1081 * so this configuration is fine too. SST25VF064C (id = 0x4b) is an
1082 * exception.
1083 */
1084 if (flash && flash->vendor == VENDOR_ID_SST && (flash->model & 0x00ff) != 0x4b)
1085 spi_config = &spi_config_aai_write;
1086
1087 if (spi_locked())
1088 return;
1089
1090 intel_southbridge_override_spi(spi_config);
1091
1092 spi_opprefix = spi_config->opprefixes[0]
1093 | (spi_config->opprefixes[1] << 8);
1094 writew_(spi_opprefix, cntlr.preop);
1095 for (i = 0; i < ARRAY_SIZE(spi_config->ops); i++) {
1096 optype |= (spi_config->ops[i].type & 3) << (i * 2);
1097 writeb_(spi_config->ops[i].op, &cntlr.opmenu[i]);
1098 }
1099 writew_(optype, cntlr.optype);
1100 }
1101
1102 __weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config)
1103 {
1104 }
1105
1106 static const struct spi_ctrlr spi_ctrlr = {
1107 .xfer_vector = xfer_vectors,
1108 .max_xfer_size = member_size(struct ich9_spi_regs, fdata),
1109 .flash_probe = spi_flash_programmer_probe,
1110 .flash_protect = spi_flash_protect,
1111 };
1112
1113 const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
1114 {
1115 .ctrlr = &spi_ctrlr,
1116 .bus_start = 0,
1117 .bus_end = 0,
1118 },
1119 };
1120
1121 const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
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