src/soc/qualcomm/sdm845/include/soc/qspi.h

   1 /* This file is part of the coreboot project. */
   2 /* SPDX-License-Identifier: GPL-2.0-only */
   3 #include <types.h>
   4 #include <soc/addressmap.h>
   5 #include <spi-generic.h>
   6
   7 #ifndef __SOC_QUALCOMM_SDM845_QSPI_H__
   8 #define __SOC_QUALCOMM_SDM845_QSPI_H__
   9
  10 struct sdm845_qspi_regs {
  11         u32 mstr_cfg;
  12         u32 ahb_mstr_cfg;
  13         u32 reserve_0;
  14         u32 mstr_int_en;
  15         u32 mstr_int_sts;
  16         u32 pio_xfer_ctrl;
  17         u32 pio_xfer_cfg;
  18         u32 pio_xfer_sts;
  19         u32 pio_dataout_1byte;
  20         u32 pio_dataout_4byte;
  21         u32 rd_fifo_cfg;
  22         u32 rd_fifo_sts;
  23         u32 rd_fifo_rst;
  24         u32 reserve_1[3];
  25         u32 next_dma_desc_addr;
  26         u32 current_dma_desc_addr;
  27         u32 current_mem_addr;
  28         u32 hw_version;
  29         u32 rd_fifo[16];
  30 };
  31
  32 check_member(sdm845_qspi_regs, rd_fifo, 0x50);
  33 static struct sdm845_qspi_regs * const sdm845_qspi = (void *) QSPI_BASE;
  34
  35 // MSTR_CONFIG register
  36
  37 #define TX_DATA_OE_DELAY_SHIFT 24
  38 #define TX_DATA_OE_DELAY_MASK (0x3 << TX_DATA_OE_DELAY_SHIFT)
  39 #define TX_CS_N_DELAY_SHIFT 22
  40 #define TX_CS_N_DELAY_MASK (0x3 << TX_CS_N_DELAY_SHIFT)
  41 #define TX_CLK_DELAY_SHIFT 20
  42 #define TX_CLK_DELAY_MASK (0x3 << TX_CLK_DELAY_SHIFT)
  43 #define TX_DATA_DELAY_SHIFT 18
  44 #define TX_DATA_DELAY_MASK (0x3 << TX_DATA_DELAY_SHIFT)
  45 #define LPA_BASE_SHIFT 14
  46 #define LPA_BASE_MASK (0xF << LPA_BASE_SHIFT)
  47 #define SBL_EN BIT(13)
  48 #define CHIP_SELECT_NUM BIT(12)
  49 #define SPI_MODE_SHIFT 10
  50 #define SPI_MODE_MASK (0x3 << SPI_MODE_SHIFT)
  51 #define BIG_ENDIAN_MODE BIT(9)
  52 #define DMA_ENABLE BIT(8)
  53 #define PIN_WPN BIT(7)
  54 #define PIN_HOLDN BIT(6)
  55 #define FB_CLK_EN BIT(4)
  56 #define FULL_CYCLE_MODE BIT(3)
  57
  58 // MSTR_INT_ENABLE and MSTR_INT_STATUS register
  59
  60 #define DMA_CHAIN_DONE BIT(31)
  61 #define TRANSACTION_DONE BIT(16)
  62 #define WRITE_FIFO_OVERRUN BIT(11)
  63 #define WRITE_FIFO_FULL BIT(10)
  64 #define HRESP_FROM_NOC_ERR BIT(3)
  65 #define RESP_FIFO_RDY BIT(2)
  66 #define RESP_FIFO_NOT_EMPTY BIT(1)
  67 #define RESP_FIFO_UNDERRUN BIT(0)
  68
  69 // PIO_TRANSFER_CONFIG register
  70
  71 #define TRANSFER_FRAGMENT BIT(8)
  72 #define MULTI_IO_MODE_SHIFT 1
  73 #define MULTI_IO_MODE_MASK (0x7 << MULTI_IO_MODE_SHIFT)
  74 #define TRANSFER_DIRECTION BIT(0)
  75
  76 // PIO_TRANSFER_STATUS register
  77
  78 #define WR_FIFO_BYTES_SHIFT 16
  79 #define WR_FIFO_BYTES_MASK (0xFFFF << WR_FIFO_BYTES_SHIFT)
  80
  81 // RD_FIFO_CONFIG register
  82
  83 #define CONTINUOUS_MODE BIT(0)
  84
  85 // RD_FIFO_STATUS register
  86
  87 #define FIFO_EMPTY BIT(11)
  88 #define WR_CNTS_SHIFT 4
  89 #define WR_CNTS_MASK (0x7F << WR_CNTS_SHIFT)
  90 #define RDY_64BYTE BIT(3)
  91 #define RDY_32BYTE BIT(2)
  92 #define RDY_16BYTE BIT(1)
  93 #define FIFO_RDY BIT(0)
  94
  95 // RD_FIFO_RESET register
  96
  97 #define RESET_FIFO BIT(0)
  98
  99 #define QSPI_MAX_PACKET_COUNT 0xFFC0
 100
 101 void quadspi_init(uint32_t hz);
 102 int sdm845_claim_bus(const struct spi_slave *slave);
 103 int sdm845_setup_bus(const struct spi_slave *slave);
 104 void sdm845_release_bus(const struct spi_slave *slave);
 105 int sdm845_xfer(const struct spi_slave *slave, const void *dout,
 106                 size_t out_bytes, void *din, size_t in_bytes);
 107 int sdm845_xfer_dual(const struct spi_slave *slave, const void *dout,
 108                      size_t out_bytes, void *din, size_t in_bytes);
 109 #endif /* __SOC_QUALCOMM_SDM845_QSPI_H__ */