src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h

   1 /* This file is part of the coreboot project. */
   2 /* SPDX-License-Identifier: GPL-2.0-only */
   3
   4 #ifndef __SOC_QCOM_QUP_SE_H__
   5 #define __SOC_QCOM_QUP_SE_H__
   6
   7 #include <console/console.h>
   8 #include <device/mmio.h>
   9 #include <gpio.h>
  10 #include <soc/addressmap.h>
  11 #include <stdint.h>
  12 #include <timer.h>
  13
  14 #define GENMASK(h, l)   (BIT(h + 1) - BIT(l))
  15
  16 /* GENI_OUTPUT_CTRL fields */
  17 #define DEFAULT_IO_OUTPUT_CTRL_MSK      GENMASK(6, 0)
  18
  19 /* GENI_FORCE_DEFAULT_REG fields */
  20 #define FORCE_DEFAULT   BIT(0)
  21
  22 #define GENI_FW_REVISION_RO_PROTOCOL_MASK       0x0000FF00
  23 #define GENI_FW_REVISION_RO_PROTOCOL_SHIFT      0x00000008
  24
  25 /* GENI_CGC_CTRL fields */
  26 #define CFG_AHB_CLK_CGC_ON              BIT(0)
  27 #define CFG_AHB_WR_ACLK_CGC_ON          BIT(1)
  28 #define DATA_AHB_CLK_CGC_ON             BIT(2)
  29 #define SCLK_CGC_ON                     BIT(3)
  30 #define TX_CLK_CGC_ON                   BIT(4)
  31 #define RX_CLK_CGC_ON                   BIT(5)
  32 #define EXT_CLK_CGC_ON                  BIT(6)
  33 #define PROG_RAM_HCLK_OFF               BIT(8)
  34 #define PROG_RAM_SCLK_OFF               BIT(9)
  35 #define DEFAULT_CGC_EN          (CFG_AHB_CLK_CGC_ON | CFG_AHB_WR_ACLK_CGC_ON \
  36                         | DATA_AHB_CLK_CGC_ON | SCLK_CGC_ON \
  37                         | TX_CLK_CGC_ON | RX_CLK_CGC_ON | EXT_CLK_CGC_ON)
  38
  39 /* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */
  40 #define SER_CLK_EN                      BIT(0)
  41 #define CLK_DIV_SHFT                    4
  42 #define CLK_DIV_MSK                     (0xFFF << CLK_DIV_SHFT)
  43
  44 /* FIFO_IF_DISABLE_RO fields */
  45 #define FIFO_IF_DISABLE                 BIT(0)
  46
  47 /* FW_REVISION_RO fields */
  48 #define FW_REV_PROTOCOL_MSK     GENMASK(15, 8)
  49 #define FW_REV_PROTOCOL_SHFT    8
  50 #define FW_REV_VERSION_SHFT             0
  51
  52 /* GENI_CLK_SEL fields */
  53 #define CLK_SEL_MSK             GENMASK(2, 0)
  54
  55 /* SE_GENI_DMA_MODE_EN */
  56 #define GENI_DMA_MODE_EN        BIT(0)
  57
  58 /* GENI_M_CMD0 fields */
  59 #define M_OPCODE_MSK            GENMASK(31, 27)
  60 #define M_OPCODE_SHFT           27
  61 #define M_PARAMS_MSK            GENMASK(26, 0)
  62
  63 /* GENI_M_CMD_CTRL_REG */
  64 #define M_GENI_CMD_CANCEL       BIT(2)
  65 #define M_GENI_CMD_ABORT        BIT(1)
  66 #define M_GENI_DISABLE          BIT(0)
  67
  68 /* GENI_S_CMD0 fields */
  69 #define S_OPCODE_MSK            GENMASK(31, 27)
  70 #define S_OPCODE_SHFT           27
  71 #define S_PARAMS_MSK            GENMASK(26, 0)
  72
  73 /* GENI_S_CMD_CTRL_REG */
  74 #define S_GENI_CMD_CANCEL       BIT(2)
  75 #define S_GENI_CMD_ABORT        BIT(1)
  76 #define S_GENI_DISABLE          BIT(0)
  77
  78 /* GENI_M_IRQ_EN fields */
  79 #define M_CMD_DONE_EN           BIT(0)
  80 #define M_CMD_OVERRUN_EN        BIT(1)
  81 #define M_ILLEGAL_CMD_EN        BIT(2)
  82 #define M_CMD_FAILURE_EN        BIT(3)
  83 #define M_CMD_CANCEL_EN         BIT(4)
  84 #define M_CMD_ABORT_EN          BIT(5)
  85 #define M_TIMESTAMP_EN          BIT(6)
  86 #define M_RX_IRQ_EN             BIT(7)
  87 #define M_GP_SYNC_IRQ_0_EN      BIT(8)
  88 #define M_GP_IRQ_0_EN           BIT(9)
  89 #define M_GP_IRQ_1_EN           BIT(10)
  90 #define M_GP_IRQ_2_EN           BIT(11)
  91 #define M_GP_IRQ_3_EN           BIT(12)
  92 #define M_GP_IRQ_4_EN           BIT(13)
  93 #define M_GP_IRQ_5_EN           BIT(14)
  94 #define M_IO_DATA_DEASSERT_EN   BIT(22)
  95 #define M_IO_DATA_ASSERT_EN     BIT(23)
  96 #define M_RX_FIFO_RD_ERR_EN     BIT(24)
  97 #define M_RX_FIFO_WR_ERR_EN     BIT(25)
  98 #define M_RX_FIFO_WATERMARK_EN  BIT(26)
  99 #define M_RX_FIFO_LAST_EN       BIT(27)
 100 #define M_TX_FIFO_RD_ERR_EN     BIT(28)
 101 #define M_TX_FIFO_WR_ERR_EN     BIT(29)
 102 #define M_TX_FIFO_WATERMARK_EN  BIT(30)
 103 #define M_SEC_IRQ_EN            BIT(31)
 104 #define M_COMMON_GENI_M_IRQ_EN  (GENMASK(6, 1) | \
 105                                 M_IO_DATA_DEASSERT_EN | \
 106                                 M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \
 107                                 M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \
 108                                 M_TX_FIFO_WR_ERR_EN)
 109
 110 /* GENI_S_IRQ_EN fields */
 111 #define S_CMD_DONE_EN           BIT(0)
 112 #define S_CMD_OVERRUN_EN        BIT(1)
 113 #define S_ILLEGAL_CMD_EN        BIT(2)
 114 #define S_CMD_FAILURE_EN        BIT(3)
 115 #define S_CMD_CANCEL_EN         BIT(4)
 116 #define S_CMD_ABORT_EN          BIT(5)
 117 #define S_GP_SYNC_IRQ_0_EN      BIT(8)
 118 #define S_GP_IRQ_0_EN           BIT(9)
 119 #define S_GP_IRQ_1_EN           BIT(10)
 120 #define S_GP_IRQ_2_EN           BIT(11)
 121 #define S_GP_IRQ_3_EN           BIT(12)
 122 #define S_GP_IRQ_4_EN           BIT(13)
 123 #define S_GP_IRQ_5_EN           BIT(14)
 124 #define S_IO_DATA_DEASSERT_EN   BIT(22)
 125 #define S_IO_DATA_ASSERT_EN     BIT(23)
 126 #define S_RX_FIFO_RD_ERR_EN     BIT(24)
 127 #define S_RX_FIFO_WR_ERR_EN     BIT(25)
 128 #define S_RX_FIFO_WATERMARK_EN  BIT(26)
 129 #define S_RX_FIFO_LAST_EN       BIT(27)
 130 #define S_COMMON_GENI_S_IRQ_EN  (GENMASK(5, 1) | GENMASK(13, 9) | \
 131                                  S_RX_FIFO_RD_ERR_EN | S_RX_FIFO_WR_ERR_EN)
 132
 133 /*  GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */
 134 #define WATERMARK_MSK           GENMASK(5, 0)
 135
 136 /* GENI_TX_FIFO_STATUS fields */
 137 #define TX_FIFO_WC              GENMASK(27, 0)
 138
 139 /*  GENI_RX_FIFO_STATUS fields */
 140 #define RX_LAST                 BIT(31)
 141 #define RX_LAST_BYTE_VALID_MSK  GENMASK(30, 28)
 142 #define RX_LAST_BYTE_VALID_SHFT 28
 143 #define RX_FIFO_WC_MSK          GENMASK(24, 0)
 144
 145 /* SE_IRQ_EN fields */
 146 #define DMA_RX_IRQ_EN           BIT(0)
 147 #define DMA_TX_IRQ_EN           BIT(1)
 148 #define GENI_M_IRQ_EN           BIT(2)
 149 #define GENI_S_IRQ_EN           BIT(3)
 150
 151 /* SE_DMA_GENERAL_CFG */
 152 #define DMA_RX_CLK_CGC_ON       BIT(0)
 153 #define DMA_TX_CLK_CGC_ON       BIT(1)
 154 #define DMA_AHB_SLV_CFG_ON      BIT(2)
 155 #define AHB_SEC_SLV_CLK_CGC_ON  BIT(3)
 156 #define DUMMY_RX_NON_BUFFERABLE BIT(4)
 157 #define RX_DMA_ZERO_PADDING_EN  BIT(5)
 158 #define RX_DMA_IRQ_DELAY_MSK    GENMASK(8, 6)
 159 #define RX_DMA_IRQ_DELAY_SHFT   6
 160
 161 #define DEFAULT_SE_CLK          (19200 * KHz)
 162 #define GENI_DFS_IF_CFG_DFS_IF_EN_BMSK                  BIT(0)
 163
 164 /* FIFO BUFFER PARAMETERS */
 165 #define BYTES_PER_FIFO_WORD     4
 166 #define FIFO_WIDTH              32
 167 #define FIFO_DEPTH              16
 168 #define BITS_PER_WORD   8
 169 #define TX_WATERMARK    1
 170
 171 /* PACKING CONFIGURATION VECTOR */
 172
 173 /* start_idx:x: Bit position to move
 174  * direction:1: MSB to LSB
 175  * len:7: Represents bits-per-word = 8
 176  * stop:0: Till it's 1, FIFO bit shift continues
 177  */
 178
 179 /* Start_idx:7, direction:1, len:7, stop:0 */
 180 #define PACK_VECTOR0    0x0FE
 181 /* Start_idx:15, direction:1, len:7, stop:0 */
 182 #define PACK_VECTOR1    0x1FE
 183 /* Start_idx:23, direction:1, len:7, stop:0 */
 184 #define PACK_VECTOR2    0x2FE
 185 /* Start_idx:31, direction:1, len:7, stop:1 */
 186 #define PACK_VECTOR3    0x3FF
 187
 188 enum qup_se {
 189         QUPV3_0_SE0,
 190         QUPV3_0_SE1,
 191         QUPV3_0_SE2,
 192         QUPV3_0_SE3,
 193         QUPV3_0_SE4,
 194         QUPV3_0_SE5,
 195         QUPV3_1_SE0,
 196         QUPV3_1_SE1,
 197         QUPV3_1_SE2,
 198         QUPV3_1_SE3,
 199         QUPV3_1_SE4,
 200         QUPV3_1_SE5,
 201         QUPV3_SE_MAX,
 202 };
 203
 204 enum se_protocol {
 205         SE_PROTOCOL_SPI  = 1,
 206         SE_PROTOCOL_UART = 2,
 207         SE_PROTOCOL_I2C  = 3,
 208         SE_PROTOCOL_I3C  = 4,
 209         SE_PROTOCOL_MAX  = 5
 210 };
 211
 212 enum se_mode {
 213         NONE,
 214         GSI,
 215         FIFO,
 216         CPU_DMA,
 217         MIXED
 218 };
 219
 220 struct qup_regs {
 221         u32 geni_init_cfg_revision;
 222         u32 geni_s_init_cfg_revision;
 223         u8  _reserved1[0x10 - 0x08];
 224         u32 geni_general_cfg;
 225         u32 geni_rx_fifo_ctrl;
 226         u8  _reserved2[0x20 - 0x18];
 227         u32 geni_force_default_reg;
 228         u32 geni_output_ctrl;
 229         u32 geni_cgc_ctrl;
 230         u32 geni_char_cfg;
 231         u32 geni_char_data_n;
 232         u8  _reserved3[0x40 - 0x34];
 233         u32 geni_status;
 234         u32 geni_test_bus_ctrl;
 235         u32 geni_ser_m_clk_cfg;
 236         u32 geni_ser_s_clk_cfg;
 237         u32 geni_prog_rom_ctrl_reg;
 238         u8  _reserved4[0x60 - 0x54];
 239         u32 geni_clk_ctrl_ro;
 240         u32 fifo_if_disable_ro;
 241         u32 geni_fw_revision_ro;
 242         u32 geni_s_fw_revision_ro;
 243         u32 geni_fw_multilock_protns_ro;
 244         u32 geni_fw_multilock_msa_ro;
 245         u32 geni_fw_multilock_sp_ro;
 246         u32 geni_clk_sel;
 247         u32 geni_dfs_if_cfg;
 248         u8 _reserved5[0x100 - 0x084];
 249         u32 geni_cfg_reg0;
 250         u32 geni_cfg_reg1;
 251         u32 geni_cfg_reg2;
 252         u32 geni_cfg_reg3;
 253         u32 geni_cfg_reg4;
 254         u32 geni_cfg_reg5;
 255         u32 geni_cfg_reg6;
 256         u32 geni_cfg_reg7;
 257         u32 geni_cfg_reg8;
 258         u32 geni_cfg_reg9;
 259         u32 geni_cfg_reg10;
 260         u32 geni_cfg_reg11;
 261         u32 geni_cfg_reg12;
 262         u32 geni_cfg_reg13;
 263         u32 geni_cfg_reg14;
 264         u32 geni_cfg_reg15;
 265         u32 geni_cfg_reg16;
 266         u32 geni_cfg_reg17;
 267         u32 geni_cfg_reg18;
 268         u8  _reserved6[0x200 - 0x14C];
 269         u32 geni_cfg_reg64;
 270         u32 geni_cfg_reg65;
 271         u32 geni_cfg_reg66;
 272         u32 geni_cfg_reg67;
 273         u32 geni_cfg_reg68;
 274         u32 geni_cfg_reg69;
 275         u32 geni_cfg_reg70;
 276         u32 geni_cfg_reg71;
 277         u32 geni_cfg_reg72;
 278         u32 spi_cpha;
 279         u32 geni_cfg_reg74;
 280         u32 proto_loopback_cfg;
 281         u32 spi_cpol;
 282         u32 i2c_noise_cancellation_ctl;
 283         u32 i2c_monitor_ctl;
 284         u32 geni_cfg_reg79;
 285         u32 geni_cfg_reg80;
 286         u32 geni_cfg_reg81;
 287         u32 geni_cfg_reg82;
 288         u32 spi_demux_output_inv;
 289         u32 spi_demux_sel;
 290         u32 geni_byte_granularity;
 291         u32 geni_dma_mode_en;
 292         u32 uart_tx_trans_cfg_reg;
 293         u32 geni_tx_packing_cfg0;
 294         u32 geni_tx_packing_cfg1;
 295         union {
 296                 u32 uart_tx_word_len;
 297                 u32 spi_word_len;
 298         };
 299         union {
 300                 u32 uart_tx_stop_bit_len;
 301                 u32 i2c_tx_trans_len;
 302                 u32 spi_tx_trans_len;
 303         };
 304         union {
 305                 u32 uart_tx_trans_len;
 306                 u32 i2c_rx_trans_len;
 307                 u32 spi_rx_trans_len;
 308         };
 309         u32 spi_pre_post_cmd_dly;
 310         u32 i2c_scl_counters;
 311         u32 geni_cfg_reg95;
 312         u32 uart_rx_trans_cfg;
 313         u32 geni_rx_packing_cfg0;
 314         u32 geni_rx_packing_cfg1;
 315         u32 uart_rx_word_len;
 316         u32 geni_cfg_reg100;
 317         u32 uart_rx_stale_cnt;
 318         u32 geni_cfg_reg102;
 319         u32 geni_cfg_reg103;
 320         u32 geni_cfg_reg104;
 321         u32 uart_tx_parity_cfg;
 322         u32 uart_rx_parity_cfg;
 323         u32 uart_manual_rfr;
 324         u32 geni_cfg_reg108;
 325         u32 geni_cfg_reg109;
 326         u32 geni_cfg_reg110;
 327         u8 _reserved7[0x600 - 0x2BC];
 328         u32 geni_m_cmd0;
 329         u32 geni_m_cmd_ctrl_reg;
 330         u8  _reserved8[0x10 - 0x08];
 331         u32 geni_m_irq_status;
 332         u32 geni_m_irq_enable;
 333         u32 geni_m_irq_clear;
 334         u32 geni_m_irq_en_set;
 335         u32 geni_m_irq_en_clear;
 336         u32 geni_m_cmd_err_status;
 337         u32 geni_m_fw_err_status;
 338         u8  _reserved9[0x30 - 0x2C];
 339         u32 geni_s_cmd0;
 340         u32 geni_s_cmd_ctrl_reg;
 341         u8  _reserved10[0x40 - 0x38];
 342         u32 geni_s_irq_status;
 343         u32 geni_s_irq_enable;
 344         u32 geni_s_irq_clear;
 345         u32 geni_s_irq_en_set;
 346         u32 geni_s_irq_en_clear;
 347         u8  _reserved11[0x700 - 0x654];
 348         u32 geni_tx_fifon;
 349         u8  _reserved12[0x780 - 0x704];
 350         u32 geni_rx_fifon;
 351         u8  _reserved13[0x800 - 0x784];
 352         u32 geni_tx_fifo_status;
 353         u32 geni_rx_fifo_status;
 354         u32 geni_tx_fifo_threshold;
 355         u32 geni_tx_watermark_reg;
 356         u32 geni_rx_watermark_reg;
 357         u32 geni_rx_rfr_watermark_reg;
 358         u8  _reserved14[0x900 - 0x818];
 359         u32 geni_gp_output_reg;
 360         u8  _reserved15[0x908 - 0x904];
 361         u32 geni_ios;
 362         u32 geni_timestamp;
 363         u32 geni_m_gp_length;
 364         u32 geni_s_gp_length;
 365         u8  _reserved16[0x920 - 0x918];
 366         u32 geni_hw_irq_en;
 367         u32 geni_hw_irq_ignore_on_active;
 368         u8  _reserved17[0x930 - 0x928];
 369         u32 geni_hw_irq_cmd_param_0;
 370         u8  _reserved18[0xA00 - 0x934];
 371         u32 geni_i3c_ibi_cfg_tablen;
 372         u8  _reserved19[0xA80 - 0xA04];
 373         u32 geni_i3c_ibi_status;
 374         u32 geni_i3c_ibi_rd_data;
 375         u32 geni_i3c_ibi_search_pattern;
 376         u32 geni_i3c_ibi_search_data;
 377         u32 geni_i3c_sw_ibi_en;
 378         u32 geni_i3c_sw_ibi_en_recover;
 379         u8 _reserved20[0xC30 - 0xA98];
 380         u32 dma_tx_ptr_l;
 381         u32 dma_tx_ptr_h;
 382         u32 dma_tx_attr;
 383         u32 dma_tx_length;
 384         u32 dma_tx_irq_stat;
 385         u32 dma_tx_irq_clr;
 386         u32 dma_tx_irq_en;
 387         u32 dma_tx_irq_en_set;
 388         u32 dma_tx_irq_en_clr;
 389         u32 dma_tx_length_in;
 390         u32 dma_tx_fsm_rst;
 391         u32 dma_tx_max_burst_size;
 392         u8  _reserved21[0xD30 - 0xC60];
 393         u32 dma_rx_ptr_l;
 394         u32 dma_rx_ptr_h;
 395         u32 dma_rx_attr;
 396         u32 dma_rx_length;
 397         u32 dma_rx_irq_stat;
 398         u32 dma_rx_irq_clr;
 399         u32 dma_rx_irq_en;
 400         u32 dma_rx_irq_en_set;
 401         u32 dma_rx_irq_en_clr;
 402         u32 dma_rx_length_in;
 403         u32 dma_rx_fsm_rst;
 404         u32 dma_rx_max_burst_size;
 405         u32 dma_rx_flush;
 406         u8  _reserved22[0xE14 - 0xD64];
 407         u32 se_irq_high_priority;
 408         u32 se_gsi_event_en;
 409         u32 se_irq_en;
 410         u32 dma_if_en_ro;
 411         u32 se_hw_param_0;
 412         u32 se_hw_param_1;
 413         u32 se_hw_param_2;
 414         u32 dma_general_cfg;
 415         u8  _reserved23[0x40 - 0x34];
 416         u32 dma_debug_reg0;
 417         u32 dma_test_bus_ctrl;
 418         u32 se_top_test_bus_ctrl;
 419         u8 _reserved24[0x1000 - 0x0E4C];
 420         u32 se_geni_fw_revision;
 421         u32 se_s_fw_revision;
 422         u8 _reserved25[0x10-0x08];
 423         u32 se_geni_cfg_ramn;
 424         u8 _reserved26[0x2000 - 0x1014];
 425         u32 se_geni_clk_ctrl;
 426         u32 se_dma_if_en;
 427         u32 se_fifo_if_disable;
 428         u32 se_geni_fw_multilock_protns;
 429         u32 se_geni_fw_multilock_msa;
 430         u32 se_geni_fw_multilock_sp;
 431 };
 432 check_member(qup_regs, geni_clk_sel, 0x7C);
 433 check_member(qup_regs, geni_cfg_reg108, 0x2B0);
 434 check_member(qup_regs, geni_dma_mode_en, 0x258);
 435 check_member(qup_regs, geni_i3c_ibi_rd_data, 0xA84);
 436 check_member(qup_regs, dma_test_bus_ctrl, 0xE44);
 437 check_member(qup_regs, se_geni_cfg_ramn, 0x1010);
 438 check_member(qup_regs, se_geni_fw_multilock_sp, 0x2014);
 439
 440 struct qup {
 441         struct qup_regs *regs;
 442         gpio_t pin[6];
 443         u8 func[6];
 444 };
 445
 446 extern struct qup qup[12];
 447
 448 u32 qup_wait_for_m_irq(unsigned int bus);
 449 u32 qup_wait_for_s_irq(unsigned int bus);
 450 void qup_m_cancel_and_abort(unsigned int bus);
 451 void qup_s_cancel_and_abort(unsigned int bus);
 452 int qup_handle_transfer(unsigned int bus, const void *dout, void *din,
 453         int size);
 454
 455 #endif /* __SOC_QCOM_QUP_SE_H__ */