src/soc/qualcomm/qcs405/include/soc/clock.h

   1  /* This file is part of the coreboot project. */
   2  /* SPDX-License-Identifier: GPL-2.0-only */
   3 #include <soc/addressmap.h>
   4 #include <types.h>
   5
   6 #ifndef __SOC_QUALCOMM_QCS405_CLOCK_H__
   7 #define __SOC_QUALCOMM_QCS405_CLOCK_H__
   8
   9 #define BLSP1_AHB_CLK_ENA                       10
  10 #define BLSP2_AHB_CLK_ENA                       20
  11 #define SRC_XO_19_2MHZ                          0
  12 #define SRC_GPLL0_MAIN_800MHZ                   1
  13
  14 /**
  15  *    USB BCR registers
  16  */
  17 #define GCC_USB_HS_PHY_CFG_AHB_BCR      0x180000C
  18 #define GCC_USB_HS_BCR                  0x1841000
  19 #define GCC_USB_30_BCR                  0x1839000
  20 #define GCC_USB2A_PHY_BCR               0x180000C
  21 #define GCC_USB2_HS_PHY_ONLY_BCR        0x1841034
  22 #define GCC_QUSB2_PHY_BCR               0x184103C
  23
  24 struct qcs405_rcg {
  25         u32 cmd;
  26         u32 cfg;
  27 };
  28
  29 struct qcs405_clock {
  30         struct qcs405_rcg rcg;
  31         uint32_t m;
  32         uint32_t n;
  33         uint32_t d_2;
  34 };
  35
  36 struct qcs405_bcr {
  37         uint32_t bcr;
  38 };
  39
  40 struct qcs405_gpll {
  41         u32 mode;
  42         u32 l_val;
  43         u32 gpll_alpha_val;
  44         u32 gpll_alpha_val_u;
  45         u32 user_ctl;
  46         u32 user_ctl_u;
  47         u32 config_ctl;
  48         u32 test_ctl;
  49         u32 test_ctl_u;
  50 };
  51
  52 struct qcs405_gcc {
  53         u8 _res0[0x1000 - 0x0];
  54         u32 blsp1_bcr;
  55         u32 blsp1_sleep_cbcr;
  56         u32 blsp1_ahb_cbcr;
  57         struct qcs405_rcg gcc_blsp_uart_sim_rcg;
  58         u8 _res1[0x2000 - 0x1014];
  59         u32 blsp1_qup1_bcr;
  60         u32 blsp1_qup1_spi_apps_cbcr;
  61         u32 blsp1_qup1_i2c_apps_cbcr;
  62         struct qcs405_clock blsp1_qup1_i2c_clk;
  63         u8 _res2[0x2024 - 0x2020];
  64         struct qcs405_clock blsp1_qup1_spi_clk;
  65         u8 _res3[0x3008-0x2038];
  66         u32 blsp1_qup2_bcr;
  67         u32 blsp1_qup2_spi_apps_cbcr;
  68         u8 _res4[0x3014 - 0x3010];
  69         struct qcs405_clock blsp1_qup2_spi_clk;
  70         u32 blsp1_uart2_bcr;
  71         u32 blsp1_uart2_apps_cbcr;
  72         u32 blsp1_uart2_sim_cbcr;
  73         struct qcs405_clock blsp1_uart2_apps_clk;
  74         u8 _res5[0x4018 - 0x3048];
  75         u32 blsp1_qup3_bcr;
  76         u32 blsp1_qup3_spi_apps_cbcr;
  77         u8 _res6[0x4024 - 0x4020];
  78         struct qcs405_clock blsp1_qup3_spi_clk;
  79         u8 _res7[0x5018 - 0x4038];
  80         u32 blsp1_qup4_bcr;
  81         u32 blsp1_qup4_spi_apps_cbcr;
  82         u8 _res8[0x5024 - 0x5020];
  83         struct qcs405_clock blsp1_qup4_spi_clk;
  84         u8 _res9[0x6020 - 0x5038];
  85         u32 blsp1_qup0_bcr;
  86         u32 blsp1_qup0_spi_apps_cbcr;
  87         u8 _res10[0x6034 - 0x6028];
  88         struct qcs405_clock blsp1_qup0_spi_clk;
  89         u8 _res11[0xB000 - 0x6048];
  90         u32 blsp2_bcr;
  91         u32 blsp2_sleep_cbcr;
  92         u32 blsp2_ahb_cbcr;
  93         u8 _res12[0xC000 - 0xB00C];
  94         u32 blsp2_qup0_bcr;
  95         u32 blsp2_qup0_spi_apps_cbcr;
  96         u8 _res13[0xC024 - 0xC008];
  97         struct qcs405_clock blsp2_qup0_spi_clk;
  98         u8 _res14[0x21000 - 0xC038];
  99         struct qcs405_gpll gpll0;
 100         u8 _res15[0x45004 - 0x21024];
 101         u32 gcc_apcs_clock_branch_en_vote;
 102 };
 103
 104 struct mdss_clock_config {
 105         const char *clk_name;
 106         struct qcs405_clock *rcgr;
 107         uint32_t  *cbcr;
 108 };
 109
 110 enum clk_ctl_gpll_user_ctl {
 111         CLK_CTL_GPLL_PLLOUT_LV_EARLY_BMSK       = 0x8,
 112         CLK_CTL_GPLL_PLLOUT_AUX2_BMSK           = 0x4,
 113         CLK_CTL_GPLL_PLLOUT_AUX_BMSK            = 0x2,
 114         CLK_CTL_GPLL_PLLOUT_MAIN_BMSK           = 0x1,
 115         CLK_CTL_GPLL_PLLOUT_LV_EARLY_SHFT       = 3,
 116         CLK_CTL_GPLL_PLLOUT_AUX2_SHFT           = 2,
 117         CLK_CTL_GPLL_PLLOUT_AUX_SHFT            = 1,
 118         CLK_CTL_GPLL_PLLOUT_MAIN_SHFT           = 0,
 119 };
 120
 121 enum clk_ctl_cfg_rcgr {
 122         CLK_CTL_CFG_MODE_BMSK           = 0x3000,
 123         CLK_CTL_CFG_MODE_SHFT           = 12,
 124         CLK_CTL_CFG_SRC_SEL_BMSK        = 0x700,
 125         CLK_CTL_CFG_SRC_SEL_SHFT        = 8,
 126         CLK_CTL_CFG_SRC_DIV_BMSK        = 0x1F,
 127         CLK_CTL_CFG_SRC_DIV_SHFT        = 0
 128 };
 129
 130 enum clk_ctl_cmd_rcgr {
 131         CLK_CTL_CMD_ROOT_OFF_BMSK       = 0x80000000,
 132         CLK_CTL_CMD_ROOT_OFF_SHFT       = 31,
 133         CLK_CTL_CMD_ROOT_EN_BMSK        = 0x2,
 134         CLK_CTL_CMD_ROOT_EN_SHFT        = 1,
 135         CLK_CTL_CMD_UPDATE_BMSK         = 0x1,
 136         CLK_CTL_CMD_UPDATE_SHFT         = 0
 137 };
 138
 139 enum clk_ctl_cbcr {
 140         CLK_CTL_CBC_CLK_OFF_BMSK        = 0x80000000,
 141         CLK_CTL_CBC_CLK_OFF_SHFT        = 31,
 142         CLK_CTL_CBC_CLK_EN_BMSK         = 0x1,
 143         CLK_CTL_CBC_CLK_EN_SHFT         = 0
 144 };
 145
 146 enum clk_ctl_rcg_mnd {
 147         CLK_CTL_RCG_MND_BMSK            = 0xFFFF,
 148         CLK_CTL_RCG_MND_SHFT            = 0,
 149 };
 150
 151 enum clk_ctl_bcr {
 152         CLK_CTL_BCR_BLK_ARES_BMSK       = 0x1,
 153         CLK_CTL_BCR_BLK_ARES_SHFT       = 0,
 154 };
 155
 156 struct clock_config {
 157         uint32_t hz;
 158         uint32_t hw_ctl;
 159         uint32_t src;
 160         uint32_t div;
 161         uint32_t m;
 162         uint32_t n;
 163         uint32_t d_2;
 164 };
 165
 166 static struct qcs405_gcc *const gcc = (void *)GCC_BASE;
 167
 168 void clock_init(void);
 169 void clock_reset_aop(void);
 170 int clock_configure_qspi(uint32_t hz);
 171 int clock_reset_bcr(void *bcr_addr, bool reset);
 172 void clock_configure_uart(uint32_t hz);
 173 void clock_configure_i2c(uint32_t hz);
 174 void clock_configure_spi(int blsp, int qup, uint32_t hz);
 175 void clock_enable_uart(void);
 176 void clock_disable_uart(void);
 177 void clock_enable_spi(int blsp, int qup);
 178 void clock_disable_spi(int blsp, int qup);
 179 void clock_enable_i2c(void);
 180 void clock_disable_i2c(void);
 181
 182 #endif  // __SOC_QUALCOMM_QCS405_CLOCK_H__