src/soc/qualcomm/qcs405/clock.c

   1  /* This file is part of the coreboot project. */
   2  /* SPDX-License-Identifier: GPL-2.0-only */
   3
   4 #include <console/console.h>
   5 #include <device/mmio.h>
   6 #include <types.h>
   7 #include <commonlib/helpers.h>
   8 #include <soc/clock.h>
   9
  10 #define DIV(div) (div ? (2*div - 1) : 0)
  11 #define HALF_DIVIDER(div2x)  (div2x ? (div2x - 1) : 0)
  12
  13 struct clock_config uart_cfg[] = {
  14         {
  15                 .hz = 1843200,
  16                 .hw_ctl = 0x0,
  17                 .src = SRC_GPLL0_MAIN_800MHZ,
  18                 .div = DIV(0),
  19                 .m = 36,
  20                 .n = 15625,
  21                 .d_2 = 15625,
  22         },
  23         {
  24                 .hz = 3686400,
  25                 .hw_ctl = 0x0,
  26                 .src = SRC_GPLL0_MAIN_800MHZ,
  27                 .div = DIV(0),
  28                 .m = 72,
  29                 .n = 15625,
  30                 .d_2 = 15625,
  31         }
  32 };
  33
  34 struct clock_config i2c_cfg[] = {
  35         {
  36                 .hz = 19200000,
  37                 .hw_ctl = 0x0,
  38                 .src = SRC_XO_19_2MHZ,
  39                 .div = DIV(0),
  40         },
  41         {
  42                 .hz = 50000000,
  43                 .hw_ctl = 0x0,
  44                 .src = SRC_GPLL0_MAIN_800MHZ,
  45                 .div = DIV(32),
  46         }
  47 };
  48
  49 struct clock_config spi_cfg[] = {
  50         {
  51                 .hz = 1000000,
  52                 .hw_ctl = 0x0,
  53                 .src = SRC_XO_19_2MHZ,
  54                 .div = DIV(48),
  55         },
  56         {
  57                 .hz = 7372800,
  58                 .src = SRC_GPLL0_MAIN_800MHZ,
  59                 .div = DIV(1),
  60                 .m = 144,
  61                 .n = 15625,
  62                 .d_2 = 15625,
  63         },
  64         {
  65                 .hz = 19200000,
  66                 .hw_ctl = 0x0,
  67                 .src = SRC_XO_19_2MHZ,
  68                 .div = DIV(0),
  69         },
  70         {
  71                 .hz = 30000000,
  72                 .hw_ctl = 0x0,
  73                 .src = SRC_XO_19_2MHZ,
  74                 .div = DIV(0),
  75         },
  76         {
  77                 .hz = 50000000,
  78                 .hw_ctl = 0x0,
  79                 .src = SRC_GPLL0_MAIN_800MHZ,
  80                 .div = DIV(32),
  81         }
  82 };
  83
  84 static int clock_configure_gpll0(void)
  85 {
  86         /* Keep existing GPLL0 configuration, in RUN mode @800Mhz. */
  87         setbits32(&gcc->gpll0.user_ctl,
  88                         1 << CLK_CTL_GPLL_PLLOUT_LV_EARLY_SHFT |
  89                         1 << CLK_CTL_GPLL_PLLOUT_AUX2_SHFT |
  90                         1 << CLK_CTL_GPLL_PLLOUT_AUX_SHFT |
  91                         1 << CLK_CTL_GPLL_PLLOUT_MAIN_SHFT);
  92         return 0;
  93 }
  94
  95 static int clock_configure_mnd(struct qcs405_clock *clk, uint32_t m, uint32_t n,
  96                                 uint32_t d_2)
  97 {
  98         uint32_t reg_val;
  99
 100         /* Configure Root Clock Generator(RCG) for Dual Edge Mode */
 101         reg_val = read32(&clk->rcg.cfg);
 102         reg_val |= (2 << CLK_CTL_CFG_MODE_SHFT);
 103         write32(&clk->rcg.cfg, reg_val);
 104
 105         /* Set M/N/D config */
 106         write32(&clk->m, m & CLK_CTL_RCG_MND_BMSK);
 107         write32(&clk->n, ~(n-m) & CLK_CTL_RCG_MND_BMSK);
 108         write32(&clk->d_2, ~(d_2) & CLK_CTL_RCG_MND_BMSK);
 109
 110         return 0;
 111 }
 112
 113 static int clock_configure(struct qcs405_clock *clk,
 114                                 struct clock_config *clk_cfg,
 115                                 uint32_t hz, uint32_t num_perfs)
 116 {
 117         uint32_t reg_val;
 118         uint32_t idx;
 119
 120         for (idx = 0; idx < num_perfs; idx++)
 121                 if (hz <= clk_cfg[idx].hz)
 122                         break;
 123
 124         reg_val = (clk_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) |
 125                         (clk_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT);
 126
 127         /* Set clock config */
 128         write32(&clk->rcg.cfg, reg_val);
 129
 130         if (clk_cfg[idx].m != 0)
 131                 clock_configure_mnd(clk, clk_cfg[idx].m, clk_cfg[idx].n,
 132                                 clk_cfg[idx].d_2);
 133
 134         /* Commit config to RCG*/
 135         setbits32(&clk->rcg.cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT));
 136
 137         return 0;
 138 }
 139
 140 static bool clock_is_off(void *cbcr_addr)
 141 {
 142         return (read32(cbcr_addr) & CLK_CTL_CBC_CLK_OFF_BMSK);
 143 }
 144
 145 static int clock_enable_vote(void *cbcr_addr, void *vote_addr,
 146                                 uint32_t vote_bit)
 147 {
 148
 149         /* Set clock vote bit */
 150         setbits32(vote_addr, BIT(vote_bit));
 151
 152         /* Ensure clock is enabled */
 153         while (clock_is_off(cbcr_addr));
 154
 155         return 0;
 156 }
 157
 158 static int clock_enable(void *cbcr_addr)
 159 {
 160
 161         /* Set clock enable bit */
 162         setbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT));
 163
 164         /* Ensure clock is enabled */
 165         while (clock_is_off(cbcr_addr))
 166                 ;
 167
 168         return 0;
 169 }
 170
 171 static int clock_disable(void *cbcr_addr)
 172 {
 173
 174         /* Set clock enable bit */
 175         clrbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT));
 176         return 0;
 177 }
 178
 179 int clock_reset_bcr(void *bcr_addr, bool reset)
 180 {
 181         struct qcs405_bcr *bcr = bcr_addr;
 182
 183         if (reset)
 184                 setbits32(&bcr->bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT));
 185         else
 186                 clrbits32(&bcr->bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT));
 187
 188         return 0;
 189 }
 190
 191 void clock_configure_uart(uint32_t hz)
 192 {
 193         struct qcs405_clock *uart_clk = (struct qcs405_clock *)
 194                                         &gcc->blsp1_uart2_apps_clk;
 195
 196         clock_configure(uart_clk, uart_cfg, hz, ARRAY_SIZE(uart_cfg));
 197 }
 198
 199 void clock_configure_spi(int blsp, int qup, uint32_t hz)
 200 {
 201         struct qcs405_clock *spi_clk = 0;
 202
 203         if (blsp == 1) {
 204                 switch (qup) {
 205                 case 0:
 206                         spi_clk = (struct qcs405_clock *)
 207                                         &gcc->blsp1_qup0_spi_clk;
 208                         break;
 209                 case 1:
 210                         spi_clk = (struct qcs405_clock *)
 211                                         &gcc->blsp1_qup1_spi_clk;
 212                         break;
 213                 case 2:
 214                         spi_clk = (struct qcs405_clock *)
 215                                         &gcc->blsp1_qup2_spi_clk;
 216                         break;
 217                 case 3:
 218                         spi_clk = (struct qcs405_clock *)
 219                                         &gcc->blsp1_qup3_spi_clk;
 220                         break;
 221                 case 4:
 222                         spi_clk = (struct qcs405_clock *)
 223                                         &gcc->blsp1_qup4_spi_clk;
 224                         break;
 225                 default:
 226                         printk(BIOS_ERR, "Invalid QUP %d\n", qup);
 227                         return;
 228                 }
 229         } else if (blsp == 2) {
 230                 spi_clk = (struct qcs405_clock *)&gcc->blsp2_qup0_spi_clk;
 231         } else {
 232                 printk(BIOS_ERR, "BLSP %d not supported\n", blsp);
 233                 return;
 234         }
 235
 236         clock_configure(spi_clk, spi_cfg, hz, ARRAY_SIZE(spi_cfg));
 237 }
 238
 239 void clock_configure_i2c(uint32_t hz)
 240 {
 241         struct qcs405_clock *i2c_clk =
 242                         (struct qcs405_clock *)&gcc->blsp1_qup1_i2c_clk;
 243
 244         clock_configure(i2c_clk, i2c_cfg, hz, ARRAY_SIZE(i2c_cfg));
 245 }
 246
 247 void clock_enable_uart(void)
 248 {
 249         clock_enable(&gcc->blsp1_uart2_apps_cbcr);
 250 }
 251
 252 void clock_disable_uart(void)
 253 {
 254         clock_disable(&gcc->blsp1_uart2_apps_cbcr);
 255 }
 256
 257 void clock_enable_spi(int blsp, int qup)
 258 {
 259         if (blsp == 1) {
 260                 switch (qup) {
 261                 case 0:
 262                         clock_enable(&gcc->blsp1_qup0_spi_apps_cbcr);
 263                         break;
 264                 case 1:
 265                         clock_enable(&gcc->blsp1_qup1_spi_apps_cbcr);
 266                         break;
 267                 case 2:
 268                         clock_enable(&gcc->blsp1_qup2_spi_apps_cbcr);
 269                         break;
 270                 case 3:
 271                         clock_enable(&gcc->blsp1_qup3_spi_apps_cbcr);
 272                         break;
 273                 case 4:
 274                         clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr);
 275                         break;
 276                 }
 277         } else if (blsp == 2)
 278                 clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr);
 279         else
 280                 printk(BIOS_ERR, "BLSP%d not supported\n", blsp);
 281 }
 282
 283 void clock_disable_spi(int blsp, int qup)
 284 {
 285         if (blsp == 1) {
 286                 switch (qup) {
 287                 case 0:
 288                         clock_enable(&gcc->blsp1_qup0_spi_apps_cbcr);
 289                         break;
 290                 case 1:
 291                         clock_enable(&gcc->blsp1_qup1_spi_apps_cbcr);
 292                         break;
 293                 case 2:
 294                         clock_enable(&gcc->blsp1_qup2_spi_apps_cbcr);
 295                         break;
 296                 case 3:
 297                         clock_enable(&gcc->blsp1_qup3_spi_apps_cbcr);
 298                         break;
 299                 case 4:
 300                         clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr);
 301                         break;
 302                 }
 303         } else if (blsp == 2)
 304                 clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr);
 305         else
 306                 printk(BIOS_ERR, "BLSP%d not supported\n", blsp);
 307
 308 }
 309
 310 void clock_enable_i2c(void)
 311 {
 312         clock_enable(&gcc->blsp1_qup1_i2c_apps_cbcr);
 313 }
 314
 315 void clock_disable_i2c(void)
 316 {
 317         clock_disable(&gcc->blsp1_qup1_i2c_apps_cbcr);
 318 }
 319
 320 void clock_init(void)
 321 {
 322         clock_configure_gpll0();
 323         clock_enable_vote(&gcc->blsp1_ahb_cbcr,
 324                                 &gcc->gcc_apcs_clock_branch_en_vote,
 325                                 BLSP1_AHB_CLK_ENA);
 326
 327         clock_enable_vote(&gcc->blsp2_ahb_cbcr,
 328                                 &gcc->gcc_apcs_clock_branch_en_vote,
 329                                 BLSP2_AHB_CLK_ENA);
 330 }