src/soc/intel/xeon_sp/uncore.c

   1 /* This file is part of the coreboot project. */
   2 /* SPDX-License-Identifier: GPL-2.0-or-later */
   3
   4 #include <cbmem.h>
   5 #include <console/console.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <device/pci.h>
   8 #include <device/pci_ids.h>
   9 #include <soc/iomap.h>
  10 #include <soc/pci_devs.h>
  11 #include <soc/ramstage.h>
  12 #include <soc/util.h>
  13 #include <fsp/util.h>
  14
  15 struct map_entry {
  16         uint32_t    reg;
  17         int         is_64_bit;
  18         int         is_limit;
  19         int         mask_bits;
  20         const char *description;
  21 };
  22
  23 enum {
  24         TOHM_REG,
  25         MMIOL_REG,
  26         MMCFG_BASE_REG,
  27         MMCFG_LIMIT_REG,
  28         TOLM_REG,
  29         ME_BASE_REG,
  30         ME_LIMIT_REG,
  31         TSEG_BASE_REG,
  32         TSEG_LIMIT_REG,
  33         /* Must be last. */
  34         NUM_MAP_ENTRIES
  35 };
  36
  37 static struct map_entry memory_map[NUM_MAP_ENTRIES] = {
  38                 [TOHM_REG] = MAP_ENTRY_LIMIT_64(VTD_TOHM_CSR, 26, "TOHM"),
  39                 [MMIOL_REG] = MAP_ENTRY_BASE_32(VTD_MMIOL_CSR, "MMIOL"),
  40                 [MMCFG_BASE_REG] = MAP_ENTRY_BASE_64(VTD_MMCFG_BASE_CSR, "MMCFG_BASE"),
  41                 [MMCFG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(VTD_MMCFG_LIMIT_CSR, 26, "MMCFG_LIMIT"),
  42                 [TOLM_REG] = MAP_ENTRY_LIMIT_32(VTD_TOLM_CSR, 26, "TOLM"),
  43                 [ME_BASE_REG] = MAP_ENTRY_BASE_64(VTD_ME_BASE_CSR, "ME_BASE"),
  44                 [ME_LIMIT_REG] = MAP_ENTRY_LIMIT_64(VTD_ME_LIMIT_CSR, 19, "ME_LIMIT"),
  45                 [TSEG_BASE_REG] = MAP_ENTRY_BASE_32(VTD_TSEG_BASE_CSR, "TSEGMB_BASE"),
  46                 [TSEG_LIMIT_REG] = MAP_ENTRY_LIMIT_32(VTD_TSEG_LIMIT_CSR, 20, "TSEGMB_LIMIT"),
  47 };
  48
  49 static void read_map_entry(struct device *dev, struct map_entry *entry,
  50         uint64_t *result)
  51 {
  52         uint64_t value;
  53         uint64_t mask;
  54
  55         /* All registers are on a 1MiB granularity. */
  56         mask = ((1ULL << entry->mask_bits) - 1);
  57         mask = ~mask;
  58
  59         value = 0;
  60
  61         if (entry->is_64_bit) {
  62                 value = pci_read_config32(dev, entry->reg + sizeof(uint32_t));
  63                 value <<= 32;
  64         }
  65
  66         value |= (uint64_t)pci_read_config32(dev, entry->reg);
  67         value &= mask;
  68
  69         if (entry->is_limit)
  70                 value |= ~mask;
  71
  72         *result = value;
  73 }
  74
  75 static void mc_read_map_entries(struct device *dev, uint64_t *values)
  76 {
  77         int i;
  78         for (i = 0; i < NUM_MAP_ENTRIES; i++)
  79                 read_map_entry(dev, &memory_map[i], &values[i]);
  80 }
  81
  82 static void mc_report_map_entries(struct device *dev, uint64_t *values)
  83 {
  84         int i;
  85         for (i = 0; i < NUM_MAP_ENTRIES; i++) {
  86                 printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n",
  87                        memory_map[i].description, values[i]);
  88         }
  89 }
  90
  91 /*
  92  * Host Memory Map:
  93  *
  94  * +--------------------------+ TOCM (2 pow 46 - 1)
  95  * |     Reserved             |
  96  * +--------------------------+
  97  * |     MMIOH (relocatable)  |
  98  * +--------------------------+
  99  * |     PCISeg               |
 100  * +--------------------------+ TOHM
 101  * |    High DRAM Memory      |
 102  * +--------------------------+ 4GiB (0x100000000)
 103  * +--------------------------+ 0xFFFF_FFFF
 104  * |     Firmware             |
 105  * +--------------------------+ 0xFF00_0000
 106  * |     Reserved             |
 107  * +--------------------------+ 0xFEF0_0000
 108  * |     Local xAPIC          |
 109  * +--------------------------+ 0xFEE0_0000
 110  * |     HPET/LT/TPM/Others   |
 111  * +--------------------------+ 0xFED0_0000
 112  * |     I/O xAPIC            |
 113  * +--------------------------+ 0xFEC0_0000
 114  * |     Reserved             |
 115  * +--------------------------+ 0xFEB8_0000
 116  * |     Reserved             |
 117  * +--------------------------+ 0xFEB0_0000
 118  * |     Reserved             |
 119  * +--------------------------+ 0xFE00_0000
 120  * |     MMIOL (relocatable)  |
 121  * |     P2SB PCR cfg BAR     | (0xfd000000 - 0xfdffffff
 122  * |     BAR space            | [mem 0x90000000-0xfcffffff] available for PCI devices
 123  * +--------------------------+ 0x9000_0000
 124  * |PCIe MMCFG (relocatable)  | CONFIG_MMCONF_BASE_ADDRESS 64 or 256MB
 125  * |                          | (0x80000000 - 0x8fffffff, 0x40000)
 126  * +--------------------------+ TOLM
 127  * |     MEseg (relocatable)  | 32, 64, 128 or 256 MB (0x78000000 - 0x7fffffff, 0x20000)
 128  * +--------------------------+
 129  * |     Tseg (relocatable)   | N x 8MB (0x70000000 - 0x77ffffff, 0x20000)
 130  * +--------------------------+ cbmem_top
 131  * |     Reserved - CBMEM     | (0x6fffe000 - 0x6fffffff, 0x2000)
 132  * +--------------------------+
 133  * |     Reserved - FSP       | (0x6fbfe000 - 0x6fffdfff, 0x400000)
 134  * +--------------------------+ top_of_ram (0x6fbfdfff)
 135  * |     Low DRAM Memory      |
 136  * +--------------------------+ FFFFF (1MB)
 137  * |     E & F segments       |
 138  * +--------------------------+ E0000
 139  * |     C & D segments       |
 140  * +--------------------------+ C0000
 141  * |     VGA & SMM Memory     |
 142  * +--------------------------+ A0000
 143  * |    Conventional Memory   |
 144  * |      (DOS Range)         |
 145  * +--------------------------+ 0
 146  */
 147
 148 static void mc_add_dram_resources(struct device *dev, int *res_count)
 149 {
 150         struct range_entry fsp_mem;
 151         uint64_t base_kb;
 152         uint64_t size_kb;
 153         uint64_t top_of_ram;
 154         uint64_t mc_values[NUM_MAP_ENTRIES];
 155         struct resource *resource;
 156         int index = *res_count;
 157
 158         fsp_find_reserved_memory(&fsp_mem);
 159
 160         /* Read in the MAP registers and report their values. */
 161         mc_read_map_entries(dev, &mc_values[0]);
 162         mc_report_map_entries(dev, &mc_values[0]);
 163
 164         top_of_ram = range_entry_base(&fsp_mem) - 1;
 165         printk(BIOS_SPEW, "cbmem_top: 0x%lx, fsp range: [0x%llx - 0x%llx], top_of_ram: 0x%llx\n",
 166                 (uintptr_t) cbmem_top(), range_entry_base(&fsp_mem),
 167                 range_entry_end(&fsp_mem), top_of_ram);
 168
 169         /* Conventional Memory (DOS region, 0x0 to 0x9FFFF) */
 170         base_kb = 0;
 171         size_kb = (0xa0000 >> 10);
 172         LOG_MEM_RESOURCE("legacy_ram", dev, index, base_kb, size_kb);
 173         ram_resource(dev, index++, base_kb, size_kb);
 174
 175         /* 1MB -> top_of_ram i.e., fsp_mem_base+1*/
 176         base_kb = (0x100000 >> 10);
 177         size_kb = (top_of_ram - 0xfffff) >> 10;
 178         LOG_MEM_RESOURCE("low_ram", dev, index, base_kb, size_kb);
 179         ram_resource(dev, index++, base_kb, size_kb);
 180
 181         /*
 182          * FSP meomoy, CBMem regions are already added as reserved
 183          * Add TSEG and MESEG Regions as reserved memory
 184          * src/drivers/intel/fsp2_0/memory_init.c sets CBMEM reserved size
 185          * arch_upd->BootLoaderTolumSize = cbmem_overhead_size(); == 2 * CBMEM_ROOT_MIN_SIZE
 186          *    typically 0x2000
 187          *  Example config:
 188          *  FSP_RESERVED_MEMORY_RESOURCE_HOB
 189          *     FspReservedMemoryResource Base : 6FBFE000
 190          *     FspReservedMemoryResource Size : 400000
 191          *  FSP_BOOT_LOADER_TOLUM_HOB
 192          *     FspBootLoaderTolum Base : 6FFFE000
 193          *     FspBootLoaderTolum Size : 2000
 194          */
 195
 196         /* Mark TSEG/SMM region as reserved */
 197         base_kb = (mc_values[TSEG_BASE_REG] >> 10);
 198         size_kb = (mc_values[TSEG_LIMIT_REG] - mc_values[TSEG_BASE_REG] + 1) >> 10;
 199         LOG_MEM_RESOURCE("mmio_tseg", dev, index, base_kb, size_kb);
 200         reserved_ram_resource(dev, index++, base_kb, size_kb);
 201
 202         /* Mark region between TSEG - TOLM (eg. MESEG) as reserved */
 203         if (mc_values[TSEG_LIMIT_REG] < mc_values[TOLM_REG]) {
 204                 base_kb = ((mc_values[TSEG_LIMIT_REG] + 1) >> 10);
 205                 size_kb = (mc_values[TOLM_REG] - mc_values[TSEG_LIMIT_REG]) >> 10;
 206                 LOG_MEM_RESOURCE("mmio_tolm", dev, index, base_kb, size_kb);
 207                 reserved_ram_resource(dev, index++, base_kb, size_kb);
 208         }
 209
 210         /* 4GiB -> TOHM */
 211         if (mc_values[TOHM_REG] > 0x100000000) {
 212                 base_kb = (0x100000000 >> 10);
 213                 size_kb = (mc_values[TOHM_REG] - 0x100000000 + 1) >> 10;
 214                 LOG_MEM_RESOURCE("high_ram", dev, index, base_kb, size_kb);
 215                 ram_resource(dev, index++, base_kb, size_kb);
 216         }
 217
 218         /* add MMIO CFG resource */
 219         resource = new_resource(dev, index++);
 220         resource->base = (resource_t) mc_values[MMCFG_BASE_REG];
 221         resource->size = (resource_t) (mc_values[MMCFG_LIMIT_REG] -
 222                 mc_values[MMCFG_BASE_REG] + 1);
 223         resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
 224                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 225         LOG_MEM_RESOURCE("mmiocfg_res", dev, index-1, (resource->base >> 10),
 226                 (resource->size >> 10));
 227
 228         /* add Local APIC resource */
 229         resource = new_resource(dev, index++);
 230         resource->base = LAPIC_DEFAULT_BASE;
 231         resource->size = 0x00001000;
 232         resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
 233                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 234         LOG_MEM_RESOURCE("apic_res", dev, index-1, (resource->base >> 10),
 235                 (resource->size >> 10));
 236
 237         /*
 238          * Add legacy region as reserved - 0xa000 - 1MB
 239          * Reserve everything between A segment and 1MB:
 240          *
 241          * 0xa0000 - 0xbffff: legacy VGA
 242          * 0xc0000 - 0xfffff: RAM
 243          */
 244         base_kb = VGA_BASE_ADDRESS >> 10;
 245         size_kb = VGA_BASE_SIZE >> 10;
 246         LOG_MEM_RESOURCE("legacy_mmio", dev, index, base_kb, size_kb);
 247         mmio_resource(dev, index++, base_kb, size_kb);
 248
 249         base_kb = (0xc0000 >> 10);
 250         size_kb = (0x100000 - 0xc0000) >> 10;
 251         LOG_MEM_RESOURCE("legacy_write_protect", dev, index, base_kb, size_kb);
 252         reserved_ram_resource(dev, index++, base_kb, size_kb);
 253
 254         *res_count = index;
 255 }
 256
 257 static void mmapvtd_read_resources(struct device *dev)
 258 {
 259         int index = 0;
 260
 261         /* Read standard PCI resources. */
 262         pci_dev_read_resources(dev);
 263
 264         /* Calculate and add DRAM resources. */
 265         mc_add_dram_resources(dev, &index);
 266 }
 267
 268 static void mmapvtd_init(struct device *dev)
 269 {
 270 }
 271
 272 static struct device_operations mmapvtd_ops = {
 273         .read_resources    = mmapvtd_read_resources,
 274         .set_resources     = pci_dev_set_resources,
 275         .enable_resources  = pci_dev_enable_resources,
 276         .init              = mmapvtd_init,
 277         .ops_pci           = &soc_pci_ops,
 278 };
 279
 280 static const unsigned short mmapvtd_ids[] = {
 281         MMAP_VTD_CFG_REG_DEVID, /* Memory Map/Intel® VT-d Configuration Registers */
 282         0
 283 };
 284
 285 static const struct pci_driver mmapvtd_driver __pci_driver = {
 286         .ops      = &mmapvtd_ops,
 287         .vendor   = PCI_VENDOR_ID_INTEL,
 288         .devices  = mmapvtd_ids
 289 };