1 /* This file is part of the coreboot project. */
2 /* SPDX-License-Identifier: GPL-2.0-or-later */
7 Name(\PICM, 0) // IOAPIC/8259
10 * Global ACPI memory region. This region is used for passing information
11 * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
12 * Since we don't know where this will end up in memory at ACPI compile time,
13 * we have to fix it up in coreboot's ACPI creation phase.
18 OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
19 Field (GNVS, ByteAcc, NoLock, Preserve)
22 OSYS, 16, // 0x00 - Operating System
23 SMIF, 8, // 0x02 - SMI function
24 PRM0, 8, // 0x03 - SMI function parameter
25 PRM1, 8, // 0x04 - SMI function parameter
26 SCIF, 8, // 0x05 - SCI function
27 PRM2, 8, // 0x06 - SCI function parameter
28 PRM3, 8, // 0x07 - SCI function parameter
29 LCKF, 8, // 0x08 - Global Lock function for EC
30 PRM4, 8, // 0x09 - Lock function parameter
31 PRM5, 8, // 0x0a - Lock function parameter
32 P80D, 32, // 0x0b - Debug port (IO 0x80) value
33 LIDS, 8, // 0x0f - LID state (open = 1)
34 PWRS, 8, // 0x10 - Power State (AC = 1)
35 PCNT, 8, // 0x11 - Processor count
36 TPMP, 8, // 0x12 - TPM Present and Enabled
37 TLVL, 8, // 0x13 - Throttle Level
38 PPCM, 8, // 0x14 - Maximum P-state usable by OS
39 PM1I, 64, // 0x15 - PM1 wake status bit
40 GPEI, 64, // 0x1D - GPE wake status bit
41 U2WE, 16, // 0x25 - USB2 Wake Enable Bitmap
42 U3WE, 8, // 0x27 - USB3 Wake Enable Bitmap
47 S5U0, 8, // 0x30 - Enable USB0 in S5
48 S5U1, 8, // 0x31 - Enable USB1 in S5
49 S3U0, 8, // 0x32 - Enable USB0 in S3
50 S3U1, 8, // 0x33 - Enable USB1 in S3
51 TACT, 8, // 0x34 - Thermal Active trip point
52 TPSV, 8, // 0x35 - Thermal Passive trip point
53 TCRT, 8, // 0x36 - Thermal Critical trip point
54 DPTE, 8, // 0x37 - Enable DPTF
58 CMEM, 32, // 0x50 - CBMEM TOC
59 TOLM, 32, // 0x54 - Top of Low Memory
60 CBMC, 32, // 0x58 - coreboot mem console pointer
61 MMOB, 32, // 0x5C - MMIO Base Low Base
62 MMOL, 32, // 0x60 - MMIO Base Low Limit
63 MMHB, 64, // 0x64 - MMIO Base High Base
64 MMHL, 64, // 0x6C - MMIO Base High Limit
65 TSGB, 32, // 0x74 - TSEG Base
66 TSSZ, 32, // 0x78 - TSEG Size