src/soc/intel/xeon_sp/include/soc/pmc.h

   1 /* This file is part of the coreboot project. */
   2 /* SPDX-License-Identifier: GPL-2.0-or-later */
   3
   4 #ifndef _SOC_PMC_H_
   5 #define _SOC_PMC_H_
   6
   7 /* PCI Configuration Space (D31:F2): PMC */
   8 #define PMC_ACPI_CNT            0x44
   9
  10 #define  SCI_IRQ_SEL            (7 << 0)
  11 #define  SCIS_IRQ9              0
  12 #define  SCIS_IRQ10             1
  13 #define  SCIS_IRQ11             2
  14 #define  SCIS_IRQ20             4
  15 #define  SCIS_IRQ21             5
  16 #define  SCIS_IRQ22             6
  17 #define  SCIS_IRQ23             7
  18
  19 #define SCI_IRQ_ADJUST          0
  20
  21 #endif