src/soc/intel/tigerlake/gpio.c

   1 /* This file is part of the coreboot project. */
   2 /* SPDX-License-Identifier: GPL-2.0-or-later */
   3
   4 #include <intelblocks/gpio.h>
   5 #include <intelblocks/pcr.h>
   6 #include <soc/pcr_ids.h>
   7 #include <soc/pmc.h>
   8
   9 /*
  10  * This file is created based on Intel Tiger Lake Processor PCH Datasheet
  11  * Document number: 575857
  12  * Chapter number: 27
  13  */
  14
  15 static const struct reset_mapping rst_map[] = {
  16         { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
  17         { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
  18         { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
  19 };
  20 static const struct reset_mapping rst_map_com2[] = {
  21         { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
  22         { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
  23         { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
  24         { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
  25 };
  26
  27 /*
  28  * The GPIO pinctrl driver for Tiger Lake on Linux expects 32 GPIOs per pad
  29  * group, regardless of whether or not there is a physical pad for each
  30  * exposed GPIO number.
  31  *
  32  * This results in the OS having a sparse GPIO map, and devices that need
  33  * to export an ACPI GPIO must use the OS expected number.
  34  *
  35  * Not all pins are usable as GPIO and those groups do not have a pad base.
  36  *
  37  * This layout matches the Linux kernel pinctrl map for TGL at:
  38  * linux/drivers/pinctrl/intel/pinctrl-tigerlake.c
  39  */
  40 static const struct pad_group tgl_community0_groups[] = {
  41         INTEL_GPP_BASE(GPP_B0, GPP_B0, GPP_B25, 0),                     /* GPP_B */
  42         INTEL_GPP_BASE(GPP_B0, GPP_T0, GPP_T15, 32),                    /* GPP_T */
  43         INTEL_GPP_BASE(GPP_B0, GPP_A0, GPP_A24, 64),                    /* GPP_A */
  44 };
  45
  46 static const struct pad_group tgl_community1_groups[] = {
  47         INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 96),                     /* GPP_S */
  48         INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 128),                   /* GPP_H */
  49         INTEL_GPP_BASE(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK, 160),      /* GPP_D */
  50         INTEL_GPP_BASE(GPP_S0, GPP_U0, GPP_GSPI6_CLK_LOOPBK, 192),      /* GPP_U */
  51         INTEL_GPP_BASE(GPP_S0, CNV_BTEN, vI2S2_RXD, 224),               /* GPP_VGPIO */
  52 };
  53
  54 /* This community is not visible to the OS */
  55 static const struct pad_group tgl_community2_groups[] = {
  56         INTEL_GPP(GPD0, GPD0, GPD_DRAM_RESETB),                         /* GPD */
  57 };
  58
  59 static const struct pad_group tgl_community4_groups[] = {
  60         INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 256),                   /* GPP_C */
  61         INTEL_GPP_BASE(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK, 288),          /* GPP_F */
  62         INTEL_GPP(GPP_C0, GPP_L_BKLTEN, GPP_MLK_RSTB),                  /* GPP_HVCMOS */
  63         INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK, 320),          /* GPP_E */
  64         INTEL_GPP(GPP_C0, GPP_JTAG_TDO, GPP_DBG_PMODE),                 /* GPP_JTAG */
  65 };
  66
  67 static const struct pad_group tgl_community5_groups[] = {
  68         INTEL_GPP_BASE(GPP_R0, GPP_R0, GPP_R7, 352),                    /* GPP_R */
  69         INTEL_GPP(GPP_R0, GPP_SPI_IO_2, GPP_CLK_LOOPBK),                /* GPP_SPI */
  70 };
  71
  72 static const struct pad_community tgl_communities[] = {
  73         [COMM_0] = { /* GPP B, T, A */
  74                 .port = PID_GPIOCOM0,
  75                 .first_pad = GPP_B0,
  76                 .last_pad = GPP_A24,
  77                 .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
  78                 .pad_cfg_base = PAD_CFG_BASE,
  79                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
  80                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
  81                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
  82                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
  83                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
  84                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
  85                 .name = "GPP_BTA",
  86                 .acpi_path = "\\_SB.PCI0.GPIO",
  87                 .reset_map = rst_map,
  88                 .num_reset_vals = ARRAY_SIZE(rst_map),
  89                 .groups = tgl_community0_groups,
  90                 .num_groups = ARRAY_SIZE(tgl_community0_groups),
  91         },
  92         [COMM_1] = { /* GPP S, D, H, U, VGPIO */
  93                 .port = PID_GPIOCOM1,
  94                 .first_pad = GPP_S0,
  95                 .last_pad = vI2S2_RXD,
  96                 .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
  97                 .pad_cfg_base = PAD_CFG_BASE,
  98                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
  99                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 100                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 101                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 102                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 103                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 104                 .name = "GPP_SDHU",
 105                 .acpi_path = "\\_SB.PCI0.GPIO",
 106                 .reset_map = rst_map,
 107                 .num_reset_vals = ARRAY_SIZE(rst_map),
 108                 .groups = tgl_community1_groups,
 109                 .num_groups = ARRAY_SIZE(tgl_community1_groups),
 110         },
 111         [COMM_2] = { /* GPD */
 112                 .port = PID_GPIOCOM2,
 113                 .first_pad = GPD0,
 114                 .last_pad = GPD_DRAM_RESETB,
 115                 .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
 116                 .pad_cfg_base = PAD_CFG_BASE,
 117                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
 118                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 119                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 120                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 121                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 122                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 123                 .name = "GPD",
 124                 .acpi_path = "\\_SB.PCI0.GPIO",
 125                 .reset_map = rst_map_com2,
 126                 .num_reset_vals = ARRAY_SIZE(rst_map_com2),
 127                 .groups = tgl_community2_groups,
 128                 .num_groups = ARRAY_SIZE(tgl_community2_groups),
 129         },
 130         [COMM_4] = { /* GPP F, C, HVCOS, E, JTAG */
 131                 .port = PID_GPIOCOM4,
 132                 .first_pad = GPP_C0,
 133                 .last_pad = GPP_DBG_PMODE,
 134                 .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
 135                 .pad_cfg_base = PAD_CFG_BASE,
 136                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
 137                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 138                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 139                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 140                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 141                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 142                 .name = "GPP_FCE",
 143                 .acpi_path = "\\_SB.PCI0.GPIO",
 144                 .reset_map = rst_map,
 145                 .num_reset_vals = ARRAY_SIZE(rst_map),
 146                 .groups = tgl_community4_groups,
 147                 .num_groups = ARRAY_SIZE(tgl_community4_groups),
 148         },
 149         [COMM_5] = { /* GPP R, SPI */
 150                 .port = PID_GPIOCOM5,
 151                 .first_pad = GPP_R0,
 152                 .last_pad = GPP_CLK_LOOPBK,
 153                 .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS,
 154                 .pad_cfg_base = PAD_CFG_BASE,
 155                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
 156                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 157                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 158                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 159                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 160                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 161                 .name = "GPP_CPU_VBPIO",
 162                 .acpi_path = "\\_SB.PCI0.GPIO",
 163                 .reset_map = rst_map,
 164                 .num_reset_vals = ARRAY_SIZE(rst_map),
 165                 .groups = tgl_community5_groups,
 166                 .num_groups = ARRAY_SIZE(tgl_community5_groups),
 167         }
 168 };
 169
 170 const struct pad_community *soc_gpio_get_community(size_t *num_communities)
 171 {
 172         *num_communities = ARRAY_SIZE(tgl_communities);
 173         return tgl_communities;
 174 }
 175
 176 const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
 177 {
 178         static const struct pmc_to_gpio_route routes[] = {
 179                 { PMC_GPP_B, GPP_B },
 180                 { PMC_GPP_T, GPP_T },
 181                 { PMC_GPP_A, GPP_A },
 182                 { PMC_GPP_R, GPP_R },
 183                 { PMC_GPD, GPD },
 184                 { PMC_GPP_S, GPP_S },
 185                 { PMC_GPP_H, GPP_H },
 186                 { PMC_GPP_D, GPP_D },
 187                 { PMC_GPP_U, GPP_U },
 188                 { PMC_GPP_F, GPP_F },
 189                 { PMC_GPP_C, GPP_C },
 190                 { PMC_GPP_E, GPP_E },
 191         };
 192         *num = ARRAY_SIZE(routes);
 193         return routes;
 194 }