src/soc/intel/icelake/gpio.c

   1 /* This file is part of the coreboot project. */
   2 /* SPDX-License-Identifier: GPL-2.0-or-later */
   3
   4 #include <intelblocks/gpio.h>
   5 #include <intelblocks/pcr.h>
   6 #include <soc/pcr_ids.h>
   7 #include <soc/pmc.h>
   8
   9 static const struct reset_mapping rst_map[] = {
  10         { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
  11         { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
  12         { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
  13 };
  14
  15 static const struct reset_mapping rst_map_com0[] = {
  16         { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
  17         { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
  18         { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
  19         { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
  20 };
  21
  22 /*
  23  * The GPIO driver for Icelake on Windows/Linux expects 32 GPIOs per pad
  24  * group, regardless of whether or not there is a physical pad for each
  25  * exposed GPIO number.
  26  *
  27  * This results in the OS having a sparse GPIO map, and devices that need
  28  * to export an ACPI GPIO must use the OS expected number.
  29  *
  30  * Not all pins are usable as GPIO and those groups do not have a pad base.
  31  *
  32  * This layout matches the Linux kernel pinctrl map for CNL-LP at:
  33  * linux/drivers/pinctrl/intel/pinctrl-icelake.c
  34  */
  35 static const struct pad_group icl_community0_groups[] = {
  36         INTEL_GPP_BASE(GPP_G0, GPP_G0, GPP_G7, 0),              /* GPP_G */
  37         INTEL_GPP_BASE(GPP_G0, GPP_B0, GPP_B23, 32),            /* GPP_B */
  38         INTEL_GPP(GPP_G0, GPIO_RSVD_0, GPIO_RSVD_1),
  39         INTEL_GPP_BASE(GPP_G0, GPP_A0, GPP_A23, 64),            /* GPP_A */
  40 };
  41
  42 static const struct pad_group icl_community1_groups[] = {
  43         INTEL_GPP_BASE(GPP_H0, GPP_H0, GPP_H23, 96),            /* GPP_H */
  44         INTEL_GPP_BASE(GPP_H0, GPP_D0, GPIO_RSVD_2, 128),       /* GPP_D */
  45         INTEL_GPP_BASE(GPP_H0, GPP_F0, GPP_F19, 160),           /* GPP_F */
  46 };
  47
  48 /* This community is not visible to the OS */
  49 static const struct pad_group icl_community2_groups[] = {
  50         INTEL_GPP(GPD0, GPD0, GPD11),                           /* GPD */
  51 };
  52
  53
  54 static const struct pad_group icl_community4_groups[] = {
  55         INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 224),           /* GPP_C */
  56         INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E23, 256),           /* GPP_E */
  57         INTEL_GPP(GPP_C0, GPIO_RSVD_3, GPIO_RSVD_8),
  58 };
  59
  60
  61 static const struct pad_group icl_community5_groups[] = {
  62         INTEL_GPP_BASE(GPP_R0, GPP_R0, GPP_R7, 288),            /* GPP_R */
  63         INTEL_GPP_BASE(GPP_C0, GPP_S0, GPP_S7, 320),            /* GPP_S */
  64 };
  65
  66 static const struct pad_community icl_communities[TOTAL_GPIO_COMM] = {
  67         /* GPP G, B, A */
  68         [COMM_0] = {
  69                 .port = PID_GPIOCOM0,
  70                 .first_pad = GPP_G0,
  71                 .last_pad = GPP_A23,
  72                 .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
  73                 .pad_cfg_base = PAD_CFG_BASE,
  74                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
  75                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
  76                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
  77                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
  78                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
  79                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
  80                 .name = "GPP_GBA",
  81                 .acpi_path = "\\_SB.PCI0.GPIO",
  82                 .reset_map = rst_map_com0,
  83                 .num_reset_vals = ARRAY_SIZE(rst_map_com0),
  84                 .groups = icl_community0_groups,
  85                 .num_groups = ARRAY_SIZE(icl_community0_groups),
  86         },
  87         /* GPP H, D, F */
  88         [COMM_1] = {
  89                 .port = PID_GPIOCOM1,
  90                 .first_pad = GPP_H0,
  91                 .last_pad = GPP_F19,
  92                 .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
  93                 .pad_cfg_base = PAD_CFG_BASE,
  94                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
  95                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
  96                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
  97                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
  98                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
  99                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 100                 .name = "GPP_HDF",
 101                 .acpi_path = "\\_SB.PCI0.GPIO",
 102                 .reset_map = rst_map,
 103                 .num_reset_vals = ARRAY_SIZE(rst_map),
 104                 .groups = icl_community1_groups,
 105                 .num_groups = ARRAY_SIZE(icl_community1_groups),
 106         },
 107          /* GPD */
 108         [COMM_2] = {
 109                 .port = PID_GPIOCOM2,
 110                 .first_pad = GPD0,
 111                 .last_pad = GPD11,
 112                 .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
 113                 .pad_cfg_base = PAD_CFG_BASE,
 114                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
 115                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 116                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 117                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 118                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 119                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 120                 .name = "GPD",
 121                 .acpi_path = "\\_SB.PCI0.GPIO",
 122                 .reset_map = rst_map,
 123                 .num_reset_vals = ARRAY_SIZE(rst_map),
 124                 .groups = icl_community2_groups,
 125                 .num_groups = ARRAY_SIZE(icl_community2_groups),
 126         },
 127         /* GPP C, E */
 128         [COMM_3] = {
 129                 .port = PID_GPIOCOM4,
 130                 .first_pad = GPP_C0,
 131                 .last_pad = GPP_E23,
 132                 .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
 133                 .pad_cfg_base = PAD_CFG_BASE,
 134                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
 135                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 136                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 137                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 138                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 139                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 140                 .name = "GPP_CE",
 141                 .acpi_path = "\\_SB.PCI0.GPIO",
 142                 .reset_map = rst_map,
 143                 .num_reset_vals = ARRAY_SIZE(rst_map),
 144                 .groups = icl_community4_groups,
 145                 .num_groups = ARRAY_SIZE(icl_community4_groups),
 146         },
 147         /* GPP R, S */
 148         [COMM_4] = {
 149                 .port = PID_GPIOCOM5,
 150                 .first_pad = GPP_R0,
 151                 .last_pad = GPP_S7,
 152                 .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS,
 153                 .pad_cfg_base = PAD_CFG_BASE,
 154                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
 155                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 156                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 157                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 158                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 159                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 160                 .name = "GPP_RS",
 161                 .acpi_path = "\\_SB.PCI0.GPIO",
 162                 .reset_map = rst_map,
 163                 .num_reset_vals = ARRAY_SIZE(rst_map),
 164                 .groups = icl_community5_groups,
 165                 .num_groups = ARRAY_SIZE(icl_community5_groups),
 166         }
 167 };
 168
 169 const struct pad_community *soc_gpio_get_community(size_t *num_communities)
 170 {
 171         *num_communities = ARRAY_SIZE(icl_communities);
 172         return icl_communities;
 173 }
 174
 175 const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
 176 {
 177         static const struct pmc_to_gpio_route routes[] = {
 178                 { PMC_GPP_G, GPP_G },
 179                 { PMC_GPP_B, GPP_B },
 180                 { PMC_GPP_A, GPP_A },
 181                 { PMC_GPP_H, GPP_H },
 182                 { PMC_GPP_D, GPP_D },
 183                 { PMC_GPP_F, GPP_F },
 184                 { PMC_GPD, GPD },
 185                 { PMC_GPP_C, GPP_C },
 186                 { PMC_GPP_E, GPP_E },
 187                 { PMC_GPP_R, GPP_R },
 188                 { PMC_GPP_S, GPP_S }
 189
 190         };
 191         *num = ARRAY_SIZE(routes);
 192         return routes;
 193 }