src/soc/intel/denverton_ns/bootblock/bootblock.c

   1 /* This file is part of the coreboot project. */
   2 /* SPDX-License-Identifier: GPL-2.0-or-later */
   3
   4 #include <bootblock_common.h>
   5 #include <cpu/x86/mtrr.h>
   6 #include <device/pci.h>
   7 #include <FsptUpd.h>
   8 #include <intelblocks/fast_spi.h>
   9 #include <soc/bootblock.h>
  10 #include <soc/iomap.h>
  11 #include <spi-generic.h>
  12 #include <console/console.h>
  13
  14 const FSPT_UPD temp_ram_init_params = {
  15         .FspUpdHeader = {
  16                         .Signature = 0x545F445055564E44ULL,
  17                         .Revision = 1,
  18                         .Reserved = {0},
  19         },
  20         .FsptCoreUpd = {
  21                         /*
  22                          * It is a requirement for firmware to have Firmware Interface Table
  23                          * (FIT), which contains pointers to each microcode update.
  24                          * The microcode update is loaded for all logical processors before
  25                          * cpu reset vector.
  26                          *
  27                          * All SoC since Gen-4 has above mechanism in place to load microcode
  28                          * even before hitting CPU reset vector. Hence skipping FSP-T loading
  29                          * microcode after CPU reset by passing '0' value to
  30                          * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength.
  31                          */
  32                         .MicrocodeRegionBase = 0,
  33                         .MicrocodeRegionLength = 0,
  34                         .CodeRegionBase =
  35                                 (UINT32)(0x100000000ULL - CONFIG_ROM_SIZE),
  36                         .CodeRegionLength = (UINT32)CONFIG_ROM_SIZE,
  37                         .Reserved1 = {0},
  38         },
  39         .FsptConfig = {
  40                         .PcdFsptPort80RouteDisable = 0,
  41                         .ReservedTempRamInitUpd = {0},
  42         },
  43         .UnusedUpdSpace0 = {0},
  44         .UpdTerminator = 0x55AA,
  45 };
  46
  47 asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
  48 {
  49         /* Call lib/bootblock.c main */
  50         bootblock_main_with_basetime(base_timestamp);
  51 };
  52
  53 void bootblock_soc_early_init(void)
  54 {
  55
  56 #if (CONFIG(CONSOLE_SERIAL))
  57         early_uart_init();
  58 #endif
  59 };
  60
  61 void bootblock_soc_init(void)
  62 {
  63         if (CONFIG(BOOTBLOCK_CONSOLE))
  64                 printk(BIOS_DEBUG, "FSP TempRamInit successful...\n");
  65 };